AT25160N-10SI-2.7 Atmel, AT25160N-10SI-2.7 Datasheet - Page 9

IC EEPROM 16KBIT 3MHZ 8SOIC

AT25160N-10SI-2.7

Manufacturer Part Number
AT25160N-10SI-2.7
Description
IC EEPROM 16KBIT 3MHZ 8SOIC
Manufacturer
Atmel
Datasheet

Specifications of AT25160N-10SI-2.7

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
16K (2K x 8)
Speed
2.1MHz, 3MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT25160N-10SI-2.7
Manufacturer:
ATM
Quantity:
50
Part Number:
AT25160N-10SI-2.7
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
0675M–SEEPR–9/03
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of
four levels of protection. The AT25080/160/320/640 is divided into four array segments. One
quarter (1/4), one half (1/2), or all of the memory segments can be protected. Any of the data
within any selected segment will therefore be READ only. The block write protection levels and
corresponding status register control bits are shown in Table 4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and
functions as the regular memory cells (e.g. WREN, t
Table 4. Block Write Protect Bits
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin
through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled
when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when
either the WP pin is high or the WPEN bit is “0”. When the device is hardware write protected,
writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-
protected sections in the memory array are disabled. Writes are only allowed to sections of the
memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as
long as the WP pin is held low.
Table 5. WPEN Operation
Level
1(1/4)
2(1/2)
3(All)
WPEN
0
X
X
0
0
1
1
BP1
Register Bits
0
0
1
1
High
High
Low
Low
WP
Status
X
X
BP0
0
1
0
1
WEN
0
1
0
1
0
1
AT25080
-03FF
-03FF
-03FF
None
0300
0200
0000
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Blocks
Array Addresses Protected
AT25160
WC
-07FF
-07FF
-07FF
None
0600
0400
0000
AT25080/160/320/640
, RDSR).
Unprotected
Protected
Protected
Protected
Writable
Writable
Writable
Blocks
AT25320
-0FFF
-0FFF
-0FFF
None
0C00
0800
0000
Protected
Protected
Protected
Protected
Register
Writable
Writable
Status
AT25640
-1FFF
-1FFF
-1FFF
None
1800
1000
0000
9

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