AT28C040-25FI Atmel, AT28C040-25FI Datasheet

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AT28C040-25FI

Manufacturer Part Number
AT28C040-25FI
Description
IC EEPROM 4MBIT 250NS 32FP
Manufacturer
Atmel
Datasheet

Specifications of AT28C040-25FI

Format - Memory
EEPROMs - Parallel
Memory Type
EEPROM
Memory Size
4M (512K x 8)
Speed
250ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
32-Flatpack
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT28C04025FI
Features
1. Description
The AT28C040 is a high-performance electrically erasable and programmable read-
only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 440 mW.
The AT28C040 is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 256-byte page register to allow
writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to
256 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by Data Polling of I/O7. Once the end of a write cycle has been detected, a
new access for a read or write can begin.
Atmel's AT28C040 has additional features to ensure high quality and manufacturabil-
ity. The device utilizes internal error correction for extended endurance and improved
data retention characteristics. An optional software data protection mechanism is
available to guard against inadvertent writes. The device also includes an extra 256
bytes of EEPROM for device identification or tracking.
Read Access Time – 200 ns
Automatic Page Write Operation
Fast Write Cycle Time
Low Power Dissipation
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
– Internal Address and Data Latches for 256 Bytes
– Internal Control Timer
– Page Write Cycle Time – 10 ms Maximum
– 1 to 256 Byte Page Write Operation
– 50 mA Active Current
– Endurance: 10,000 Cycles
– Data Retention: 10 Years
4-Megabit
(512K x 8)
Paged Parallel
EEPROMs
AT28C040
0542F–PEEPR–2/09

Related parts for AT28C040-25FI

AT28C040-25FI Summary of contents

Page 1

... Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 440 mW. The AT28C040 is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 256-byte page register to allow writing 256 bytes simultaneously ...

Page 2

... Pin Name Function A0 - A18 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect 2.1 44-lead LCC – Top View A12 AT28C040 2 2.2 32-lead Flatpack – Top View 39 A13 A11 A10 29 CE A18 1 32 VCC A16 A15 3 30 A17 ...

Page 3

... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. + 0.6V CC AT28C040 3 ...

Page 4

... Read The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either high. This dual-line control gives designers flexibility in preventing bus contention in their systems ...

Page 5

... After writing the 3-byte command sequence and after t protected against inadvertent write operations. It should be noted that once protected, the host can still perform a byte or page write to the AT28C040 so, the same 3-byte command sequence used to enable SDP must precede the data to be written. ...

Page 6

... Extended -55°C - 125°C 5V ± 10 Condition I MHz OUT -400 µ -100 µ 4. AT28C040-20 Operation Read Program -40°C - 85°C -40°C - 85°C 5V ± 10 Min Max 0.8 2.0 0.45 2.4 4.2 0542F–PEEPR–2/09 I/O D OUT D IN High Z Units µA µ ...

Page 7

... Note: 1. This parameter is characterized and is not 100% tested. 0542F–PEEPR–2/09 (1)(2)(3)( after the address transition without impact on t ACC after the falling edge of CE without impact pF). L Max 10 12 AT28C040 AT28C040-20 Min Max 200 200 ACC after an address change CE ACC OE ...

Page 8

... OES t Address Hold Time AH t Chip Select Set-up Time CS t Chip Select Hold Time CH t Write Pulse Width ( Data Set-up Time Data, OE Hold Time DH OEH 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled AT28C040 8 Min Max Units 100 0542F–PEEPR–2/09 ...

Page 9

... Write Pulse Width High WPH 17. Page Mode Write Waveforms Notes through A18 must specify the page address during each high to low transition of WE (or CE must be high only when WE and CE are both low. 0542F–PEEPR–2/09 Min 100 50 (1)(2) AT28C040 Max Units μs 150 ns 9 ...

Page 10

... A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must be the same for each high to low transition of WE (or CE must be high only when WE and CE are both low. AT28C040 10 19. Software Data (1) ...

Page 11

... Toggle Bit Waveforms Notes: 1. Toggling either both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 0542F–PEEPR–2/09 (1) (1) (1)(2)(3) AT28C040 Min Typ Max Min Typ ...

Page 12

... Standard Packaging I (mA ACC (ns) Active 50 200 AT28C040-20FI SL703 50 AT28C040-20LI SL703 Note: 1. SL703 requires testing to Mil-883 standards; SL703 is marked on the package. 32F 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 44L 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms ...

Page 13

... Orchard Parkway San Jose, CA 95131 R 0542F–PEEPR–2/09 PIN #1 ID 0.18(0.007) 0.10(0.004) 9.02(0.355) 1.83(0.072) 0.76(0.030) TITLE 32F, 32-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (FlatPack) AT28C040 9.40(0.370) 6.86(0.270) 0.51(0.020) 0.38(0.015) 1.27(0.050) BSC 1.14(0.045) MAX 3.05(0.120) 2.49(0.098) 1.14(0.045) 0.66(0.026) DRAWING NO. 32F 10/21/03 REV ...

Page 14

... LCC Dimensions in Millimeters and (Inches) Controlling dimension: Inches MIL-STD-1835 C-5 16.81(0.662) 16.26(0.640) 12.70(0.500) BSC 1.27(0.050) TYP 2325 Orchard Parkway San Jose, CA 95131 R AT28C040 14 16.81(0.662) 16.26(0.640) PIN 1 1.40(0.055) 1.14(0.045) 2.41(0.095) 1.91(0.075) 12.70(0.500) BSC TITLE 44L, 44-pad (0.600" Wide), Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) 2 ...

Page 15

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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