MT29F2G16AABWP-ET Micron Technology Inc, MT29F2G16AABWP-ET Datasheet - Page 29
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MT29F2G16AABWP-ET
Manufacturer Part Number
MT29F2G16AABWP-ET
Description
IC FLASH 2GBIT 48TSOP
Manufacturer
Micron Technology Inc
Datasheet
1.MT29F2G08AAAWP.pdf
(57 pages)
Specifications of MT29F2G16AABWP-ET
Format - Memory
FLASH
Memory Type
FLASH - Nand
Memory Size
2G (128M x 16)
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Speed
-
Other names
557-1151-2
PROGRAM Operations
PROGRAM PAGE 80h-10h
SERIAL DATA INPUT 80h
RANDOM DATA INPUT 85h
Figure 23:
Figure 24:
PDF: 09005aef818a56a7 / Source: 09005aef81590bdd
2gb_nand_m29b__2.fm - Rev. I 1/06 EN
R/B#
I/Ox
R/B#
I/Ox
80h
80h
PROGRAM and READ STATUS Operation
RANDOM DATA INPUT
Address (5 cycles)
Address (5 cycles)
Micron NAND Flash devices are inherently page-programmed devices. Within a block,
the pages must be programmed consecutively from the least significant bit (LSB) page of
the block to most significant bit (MSB) pages of the block. Random page address pro-
gramming is prohibited.
Micron NAND flash devices also support partial-page programming operations. This
means that any single bit can only be programmed one time before an erase is required;
however, the page can be partitioned such that a maximum of eight programming oper-
ations are allowed before an erase is required.
PAGE PROGRAM operations require loading the SERIAL DATA INPUT (80h) command
into the command register, followed by five ADDRESS cycles, then the data. Serial data
is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h)
command is written after the data input is complete. The internal write state machine
automatically executes the proper algorithm and controls all the necessary timing to
program and verify the operation. Write verification only detects “1s” that are not suc-
cessfully written to “0s.”
R/B# goes LOW for the duration of array programming time,
REGISTER (70h) command and the RESET (FFh) command are the only commands valid
during the programming operation. Bit 6 of the status register will reflect the state of
R/B#. When the device reaches ready, read bit 0 of the status register to determine if the
program operation passed or failed. (See Figure 23.) The command register stays in read
status register mode until another valid command is written to it.
After the initial data set is input, additional data can be written to a new column address
with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT com-
mand can be used any number of times in the same page prior to issuing the PAGE
WRITE (10h) command. See Figure 24 for the proper command sequence.
D
IN
D
85h
IN
Address (2 cycles)
10h
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
t PROG
29
D
IN
10h
Micron Technology, Inc., reserves the right to change products or specifications without notice.
70h
t PROG
I/O 0 = 0 PROGRAM successful
I/O 0 = 1 PROGRAM error
Command Definitions
t
Status
70h
PROG. The READ STATUS
©2004 Micron Technology, Inc. All rights reserved.
Status