MT28F008B3VG-9 B TR Micron Technology Inc, MT28F008B3VG-9 B TR Datasheet - Page 8

• Manufacturer Part Number: MT28F008B3VG-9 B TR
• Description: IC FLASH 8MBIT 90NS 40TSOP
• Manufacturer: Micron Technology Inc

Specifications of MT28F008B3VG-9 B TR

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 8M (1M x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

task and when an ERASE has been suspended. Addi-
tional error information is set in three other bits: V
status, write status and erase status.
Command Execution Logic (CEL)
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register
or status register). Commands may be issued to the
CEL while the ISM is active. However, there are restric-
tions on what commands are allowed in this condition.
See the Command Execution section for more detail.
Deep Power-Down Mode
current, deep power-down mode. To enter this mode,
the RP# pin is taken to V
rent draw is a maximum of 8µA at 3.3V V
deep power-down also clears the status register and
sets the ISM to the read array mode.
Memory Architecture
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into eleven addressable blocks that vary in size
and are independently erasable. When blocks rather
than the entire array are erased, total device endur-
ance is enhanced, as is system flexibility. Only the
09005aef81136a91
Q10.fm - Rev. E 6/04 EN
The CEL receives and interprets commands to the
To allow for maximum power conservation, the
MT28F800B3 and MT28F008B3 feature a very low
The MT28F800B3 and MT28F008B3 memory array
WORD ADDRESS
70000h
60000h
50000h
40000h
30000h
20000h
10000h
04000h
03000h
02000h
00000h
03FFFh
02FFFh
01FFFh
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
SS
±0.2V. In this mode, the cur-
MT28F008B3/800B3xx-xxB
BYTE ADDRESS
Bottom Boot
A0000h
C0000h
E0000h
DFFFFh
80000h
60000h
40000h
20000h
08000h
06000h
04000h
00000h
BFFFFh
07FFFh
05FFFh
03FFFh
FFFFFh
9FFFFh
7FFFFh
5FFFFh
3FFFFh
1FFFFh
Figure 3: Memory Address Maps
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
CC
. Entering
SMART 3 BOOT BLOCK FLASH MEMORY
PP
8
ERASE function is block-oriented. All READ and
WRITE operations are done on a random-access basis.
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP#
or that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining ten blocks do not require that either of
these two conditions be met before WRITE or ERASE
operations.
Boot Block
security for the most sensitive portions of the firm-
ware. This 16KB block may only be erased or written
when the RP# pin is at the specified boot block unlock
voltage (V
During a WRITE or ERASE of the boot block, the RP#
pin must be held at V
until the WRITE or ERASE is completed. (The WP# pin
does not apply to the SOP package.) The V
be at V
to or erased.
in two configurations and top or bottom boot block.
The top boot block version supports processors of the
x86 variety. The bottom boot block version is
intended for 680X0 and RISC applications. Figure 3
illustrates the memory address maps associated with
these two versions.
WORD ADDRESS
The boot block is protected from unintentional
The hardware-protected boot block provides extra
The MT28F800B3 and MT28F008B3 are available
7D000h
7C000h
7E000h
7DFFFh
7CFFFh
7BFFFh
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PPH
MT28F008B3/800B3xx-xxT
HH
(3.3V or 5V) when the boot block is written
BYTE ADDRESS
) of 12V or when the WP# pin is HIGH.
FA000h
A0000h
Top Boot
FC000h
E0000h
C0000h
80000h
60000h
40000h
20000h
00000h
F8000h
DFFFFh
FBFFFh
F9FFFh
F7FFFh
BFFFFh
9FFFFh
7FFFFh
5FFFFh
3FFFFh
1FFFFh
FFFFFh
8KB Parameter Block
8KB Parameter Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
128KB Main Block
96KB Main Block
16KB Boot Block
HH
or the WP# pin held HIGH
©2001 Micron Technology, Inc. All rights reserved.
PP
8Mb
pin must