MT45W4MW16BFB-708 WT F Micron Technology Inc, MT45W4MW16BFB-708 WT F Datasheet - Page 17
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MT45W4MW16BFB-708 WT F
Manufacturer Part Number
MT45W4MW16BFB-708 WT F
Description
IC PSRAM 64MBIT 70NS 54VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT45W4MW16BBB-706_WT_TR.pdf
(61 pages)
Specifications of MT45W4MW16BFB-708 WT F
Format - Memory
RAM
Memory Type
PSRAM (Page)
Memory Size
64M (4M x 16)
Speed
70ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-30°C ~ 85°C
Package / Case
54-VFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Configuration Registers
Access Using CRE
Figure 13:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
(except A19)
DQ[15:0]
LB#/UB#
A[21:0]
Configuration Register WRITE in Asynchronous Mode Followed by READ ARRAY
ADV#
A19
WE#
OE#
CLK
CRE
CE#
1
Note:
Two user-accessible configuration registers define the device operation. The bus config-
uration register (BCR) defines how the CellularRAM interacts with the system memory bus
and is nearly identical to its counterpart on burst mode Flash devices. The refresh configu-
ration register (RCR) is used to control how refresh is performed on the DRAM array.
These registers are automatically loaded with default settings during power-up, and can
be updated any time the devices are operating in a standby state.
The configuration registers are loaded using either a synchronous or an asynchronous
WRITE operation when the control register enable (CRE) input is HIGH (see Figure 13
below and Figure 14 on page 18). When CRE is LOW, a READ or WRITE operation will
access the memory array. The register values are placed on addresses A[21:0]. In an asyn-
chronous WRITE, the values are latched into the configuration register on the rising
edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care.” Access
using CRE is WRITE only. The BCR is accessed when A[19] is HIGH; the RCR is accessed
when A[19] is LOW.
t VPH
Select Control Register
Operation
A[19] = LOW to load RCR; A[19] = HIGH to load BCR.
OPCODE
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
t AVS
t AVS
Initiate Control Register Access
t VP
t AVH
t AVH
t CW
Write Address Bus Value
17
to Control Register
t WP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t CBPH
ADDRESS
ADDRESS
Configuration Registers
©2003 Micron Technology, Inc. All rights reserved.
DATA VALID
DON’T CARE