MT47H256M4BT-3:A Micron Technology Inc, MT47H256M4BT-3:A Datasheet - Page 96
![IC DDR2 SDRAM 1GBIT 3NS 92FBGA](/photos/7/26/72643/557-92-fbga_sml.jpg)
MT47H256M4BT-3:A
Manufacturer Part Number
MT47H256M4BT-3:A
Description
IC DDR2 SDRAM 1GBIT 3NS 92FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H256M4HQ-5EE_TR.pdf
(131 pages)
Specifications of MT47H256M4BT-3:A
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (256M x 4)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
92-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H256M4BT-3:A
Manufacturer:
Micron Technology Inc
Quantity:
10 000
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READ with Auto Precharge
Table 41: READ Using Concurrent Auto Precharge
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
From Command (Bank n)
READ with auto precharge
If A10 is high when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock
edge that is AL + (BL/2) cycles later than the read with auto precharge command provi-
ded
edge, the start point of the auto precharge operation will be delayed until
satisfied. If
auto precharge operation will be delayed until
nal precharge is pushed out by
charge happens (not at the next rising clock edge after this event).
When BL = 4, the minimum time from READ with auto precharge to the next ACTIVATE
command is AL + (
auto precharge to the next ACTIVATE command is AL + 2 clocks + (
term (
tion can also be used: AL + BL/2 - 2CK + (
precharge does not start earlier than two clocks after the last 4-bit prefetch.
READ with auto precharge command may be applied to one bank while another bank is
operational. This is referred to as concurrent auto precharge operation, as noted in Ta-
ble 41. Examples of READ with precharge and READ with auto precharge with applica-
ble timing requirements are shown in Figure 52 (page 97) and Figure 53 (page 98),
respectively.
t
WRITE or WRITE with auto precharge
RAS (MIN) and
READ or READ with auto precharge
t
RTP +
PRECHARGE or ACTIVATE
To Command (Bank m)
t
RTP (MIN) is not satisfied at this rising clock edge, the start point of the
t
RP)/
t
t
CK is always rounded up to the next integer. A general purpose equa-
RTP +
t
RTP are satisfied. If
t
RP)/
96
t
t
CK. When BL = 8, the minimum time from READ with
RTP,
t
RP starts at the point where the internal pre-
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
RAS (MIN) is not satisfied at this rising clock
RTP +
(with Concurrent Auto Precharge)
1Gb: x4, x8, x16 DDR2 SDRAM
t
RTP (MIN) is satisfied. When the inter-
t
RP)/
Minimum Delay
t
CK. In any event, the internal
(BL/2) + 2
BL/2
1
© 2004 Micron Technology, Inc. All rights reserved.
t
RTP +
t
t
RAS (MIN) is
RP)/
t
CK. The
READ
Units
t
t
t
CK
CK
CK
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