MT48H8M32LFB5-10 IT Micron Technology Inc, MT48H8M32LFB5-10 IT Datasheet
MT48H8M32LFB5-10 IT
Specifications of MT48H8M32LFB5-10 IT
Related parts for MT48H8M32LFB5-10 IT
MT48H8M32LFB5-10 IT Summary of contents
Page 1
MOBILE SDRAM Features • Low voltage power supply • Partial Array Self Refresh power-saving mode • Temperature Compensated Self Refresh (TCSR) • Deep power-down mode • Programmable Output Drive Strength • Fully synchronous; all signals registered on positive edge of ...
Page 2
Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
List of Figures Figure 1: Pin Assignment (Top View) 90-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
List of Tables Table 1: Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
... MT48H8M32LFF5-10 1.8V/1.8V MT48H8M32LFB5-8 1.8V/1.8V 1.8V/1.8V MT48H8M32LFB5-10 FBGA Part Number System Due to space limitations, FBGA-packaged compo- nents have an abbreviated part marking that is differ- ent from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on the Micron web site, www ...
Page 6
... MOBILE SDRAM BA1 BA0 Bank BANK3 BANK2 BANK1 BANK0 MEMORY 4 ARRAY DATA OUTPUT 32 REGISTER 4096 DATA INPUT 32 512 REGISTER (x32) COLUMN DECODER Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. ...
Page 7
... Input Address Inputs: A0–A11 are sampled during the ACTIVE command (row- address A0–A11) and READ/WRITE command (column-address A0–A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 ...
Page 8
Functional Description In general, the 256Mb SDRAMs (2 Meg banks) are quad-bank DRAMs that operate at 3.3V, 2.5V, and 1.8V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, ...
Page 9
A3–A8 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full- page bursts wrap within the page if the boundary is reached. Burst Type ...
Page 10
CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks. If ...
Page 11
... RFU For further power savings during SELF REFRESH, the Partial Array Self Refresh (PASR) feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are all banks (banks and 3); two banks (banks 0 and 1); and one bank (bank 0). Also included in the refresh options are the half-bank and quarter-bank partial array self refresh (bank 0) ...
Page 12
Commands Table Table 7:, Truth Table – Commands and DQM Operation, provides a quick reference of available commands. This is followed by a written description of Table 7: Truth Table – Commands and DQM Operation CKE is HIGH for all ...
Page 13
... Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data given DQM signal is reg- istered LOW, the corresponding data will be written to memory ...
Page 14
... DEEP POWER DOWN Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices. Array data will not be retained once the device enters Deep Power Down Mode. The settings in the Mode and Extended Mode register will be retained during Deep Power- down ...
Page 15
Operation Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the ...
Page 16
READs READ bursts are initiated with a READ command, as shown in Figure 8. The starting column and bank addresses are pro- vided with the READ command, and auto precharge is either enabled or disabled for that burst access. If ...
Page 17
This is shown in Figure 10 for CAS latencies of one, two and three; data element either the last of a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses ...
Page 18
CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 11: Random READ ...
Page 19
Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may be immediately followed by data from a WRITE command (subject to bus turn- around limitations). The WRITE burst ...
Page 20
CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: DQM is LOW. pdf: 09005aef80d460f2, source: 09005aef80cd8d41 256Mb SDRAM x32_2.fm - Rev. D 9/04 EN Figure 14: READ to PRECHARGE READ NOP ...
Page 21
Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMI- NATE command, provided that auto precharge was not activated. The BURST TERMINATE command Figure 15: Terminating a READ ...
Page 22
WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 16. The starting column and bank addresses are pro- vided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto ...
Page 23
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed- length WRITE burst may be immediately followed by a READ command. Once the READ command is regis- tered, the data inputs will ...
Page 24
... DEEP POWER-DOWN Deep Power Down mode is a maximum power sav- ings feature achieved by shutting off the power to the entire memory array of the device. Data on the mem- ory array will not be retained once Deep Power Down mode is executed. Deep Power Down mode is entered ...
Page 25
In order to exit Deep Power Down mode, CKE must be asserted high. After exiting, the following sequence is needed in order to enter a new command: Maintain NOP input conditions for a minimum of 100us. Issue PRECHARGE commands for ...
Page 26
Figure 27: READ With Auto Precharge Interrupted by a READ COMMAND BANK n Internal States BANK m ADDRESS NOTE: DQM is LOW. Figure 28: READ With Auto Precharge Interrupted by a WRITE COMMAND BANK n Internal States BANK m ADDRESS ...
Page 27
WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto pre- charge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The precharge to t ...
Page 28
Table 8: Truth Table – CKE Notes: 1-4 CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend Deep Power-Down L H Power-Down Deep Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle ...
Page 29
Table 9: Truth Table – Current State Bank n, Command To Bank n Notes: 1-6; notes appear below table CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) Any Idle ...
Page 30
Refreshing: Starts with registration of an AUTO REFRESH command and ends when SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when t been met. Once ...
Page 31
Table 10: Truth Table – Current State Bank n, Command To Bank m Notes: 1-6; notes appear below and on next page CURRENT RAS CAS STATE CS Any Idle ...
Page 32
READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge ...
Page 33
Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
Page 34
Table 13: DC Electrical Characteristics and Operating Conditions H Version Notes notes appear on page 39; V PARAMETER/CONDITION Supply Voltage I/O Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs ...
Page 35
Table 14: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; notes appear on page 39 AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level ...
Page 36
Table 15: AC Functional Characteristics Notes 11; notes appear on page 39 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode ...
Page 37
Table 17: I Specifications and Conditions – V Version DD Notes 11, 13; notes appear on page 39; V PARAMETER/CONDITION Operating Current: Active Mode; Burst = 2; READ or WRITE (MIN) Standby ...
Page 38
Table 19 Self Refresh Current Options DD Note: 4; notes appear on page 39 TEMPERATURE COMPENSATED SELF REFRESH PARAMETER/CONDITION Self Refresh Current: CKE = LOW -- 4 Bank Refresh Self Refresh Current: CKE = LOW -- 2 ...
Page 39
Notes 1. All voltages referenced This parameter is sampled. V 2.5V or 3.3V 25°C; pin under test biased at A 1.4V MHz dependent on output loading and cycle I ...
Page 40
Figure 31: Initialize And Load Mode Register CLK ( ( ) ) t t CKS CKH ( ( ) ) CKE ( ( ) ) t t CMS CMH ( ( ) ) 5 COMMAND ...
Page 41
CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQML, DQMU A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all All banks ...
Page 42
CLK CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQMU, DQML A0-A9, A11 COLUMN A10 t ...
Page 43
T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQMU, DQML A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks NOTE: 1. Each ...
Page 44
T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQMU, DQML A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Precharge all active banks NOTE: 1. Each ...
Page 45
Figure 36: READ – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 DISABLE ...
Page 46
Figure 37: Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 t ...
Page 47
Figure 38: Single Read – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
Page 48
Figure 39: Single Read – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
Page 49
Figure 40: Alternating Bank Read Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW A10 ROW t AS ...
Page 50
CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ t CMS DQM 0 A0-A9, A11 COLUMN m 2 ROW ...
Page 51
CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...
Page 52
Figure 43: Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML A0-A9, A11 COLUMN m 3 ROW ...
Page 53
Figure 44: Write – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML COLUMN m 2 A0-A9, A11 ROW ...
Page 54
Figure 45: Single Write – Without Auto Precharge CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 ...
Page 55
Figure 46: Single Write – With Auto Precharge CLK t CKS t CKH CKE t CMS t CMH NOP 3 COMMAND ACTIVE DQMU, DQML A0-A9, A11 ROW ...
Page 56
Figure 47: Alternating Bank Write Accesses CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQMU, DQML COLUMN m 2 A0-A9, A11 ROW t ...
Page 57
CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM 0 A0-A9, A11 ROW ROW A10 BA0, BA1 ...
Page 58
CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQMU, DQML A0-A9, A11 ROW ROW A10 BA0, BA1 BANK DQ ...
Page 59
Figure 50: 90-Ball VFBGA (8mm x 13mm) 0.65 ±0.05 SEATING PLANE C 0.10 C 90X Ø0.45 ±0.05 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø0.42 BALL A9 11.20 ±0.10 5.60 ±0.05 3.20 ±0.05 8.00 ...