MT48V4M32LFF5-8:G Micron Technology Inc, MT48V4M32LFF5-8:G Datasheet - Page 57

• Manufacturer Part Number: MT48V4M32LFF5-8:G
• Description: IC SDRAM 128MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48V4M32LFF5-8:G

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every 2 clocks and are
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every 2 clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
1. All voltages are referenced to Vss.
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V (for LC devices) or at 1.25V (V devices) with equivalent
1.4V, f = 1 MHz.
with minimum cycle time and the outputs open.
operation over the full temperature range is ensured (0°C ≤ T
40°C ≤ T
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
load:
Q
t
a reference to V
High-Z.
to V
ing is referenced at V
Established tester values follow: V
devices.
otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
is dependent on output loading and cycle rates. Specified values are obtained
IH
specifications are tested after the device is properly initialized.
DD
/2 crossover point. If the input transition time is longer than 1ns, then the tim-
A
30pF
current will increase or decrease proportionally according to the amount of
t
≤
CK = 125MHz for -8 and
+85°C (industrial), and –40°C ≤ T
IH
OH
DD
and V
or V
tests use established values for V
IH
IL
IL
or V
(
OL
MAX
(or between V
. The last valid data element will meet
SS
IL
t
57
T = 1ns.
) and V
and V
levels.
t
t
t
DD
CKS; clock(s) specified as a reference only at minimum
WR plus
WR.
, V
IL
SS
DD
IH
t
CK = 100MHz for -10.
= 0V, V
Q must be at same potential.) The two AUTO
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(
Q = +3.3V; T
MIN
IL
t
RP; clock(s) specified as a reference only at
and V
) and no longer at the V
IH
128Mb: x16, x32 Mobile SDRAM
A
= 3.0V for LC devices and V
≤
IH
+105°C (automotive)).
) in a monotonic manner.
A
= 25°C; pin under test biased at
IL
and V
DD
IH
©2001 Micron Technology, Inc. All rights reserved.
A
and V
, with timing referenced
≤
t
+70°C (commercial), –
OH before going
t
IH
REF refresh require-
/2 crossover point.
DD
Q must be pow-
IH
= 2.3V for V
Notes