MT46H8M32LFB5-10 IT:A TR Micron Technology Inc, MT46H8M32LFB5-10 IT:A TR Datasheet - Page 75
![IC DDR SDRAM 256MBIT 90VFBGA](/photos/7/23/72313/mfg557-90-vfbga_sml.jpg)
MT46H8M32LFB5-10 IT:A TR
Manufacturer Part Number
MT46H8M32LFB5-10 IT:A TR
Description
IC DDR SDRAM 256MBIT 90VFBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT46H16M16LFBF-6A_TR.pdf
(79 pages)
Specifications of MT46H8M32LFB5-10 IT:A TR
Format - Memory
RAM
Memory Type
Mobile DDR SDRAM
Memory Size
256M (8Mx32)
Speed
100MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Package / Case
90-VFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Figure 47:
PDF: 09005aef82091978 / Source: 09005aef8209195b
MT46H16M16LF__2.fm - Rev. H 6/08 EN
Command
BA0, BA1
A11, A12
A0–A9
DQS
DQ
CK#
CKE
A10
DM
CK
5
1
t IS
t IS
Bank Write – Without Auto Precharge
NOP
T0
t IH
t IH
6
Notes:
Bank x
t IS
t IS t IH
ACT
RA
RA
RA
T1
7. Refer to Figures 37 and 38 on pages 66–67 for DQS and DQ timing details.
1. D
2. BL = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = row address; BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
7.
8.
t IH
order.
times.
t
t
t CK
DSH is applicable during
DSS is applicable during
IN
n = data-in from column n; subsequent elements are provided in the programmed
t RCD
NOP
T2
6
t CH
t CL
WRITE
t IS
Bank x
Col n
3
T3
t IH
t DQSS(NOM)
2
t WPRES
t
t
DQSS (MIN) and is referenced from CK T5 or T6.
DQSS (MIN) and is referenced from CK T4 or T5.
t DS
75
t WPRE
NOP
D
T4
OUT
b
6
t DH
t RAS
T4n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile DDR SDRAM
t DQSL t DQSH t WPST
NOP
T5
6
T5n
Transitioning data
NOP
T6
6
©2005 Micron Technology, Inc. All rights reserved.
Timing Diagrams
t WR
NOP
T7
6
Don’t Care
All banks
One bank
Bank x
PRE
T8
4
t RP
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