MT47H256M4BT-5E:A TR Micron Technology Inc, MT47H256M4BT-5E:A TR Datasheet - Page 55
![IC DDR2 SDRAM 1GBIT 5NS 92FBGA](/photos/7/26/72643/557-92-fbga_sml.jpg)
MT47H256M4BT-5E:A TR
Manufacturer Part Number
MT47H256M4BT-5E:A TR
Description
IC DDR2 SDRAM 1GBIT 5NS 92FBGA
Manufacturer
Micron Technology Inc
Datasheet
1.MT47H256M4HQ-5EE_TR.pdf
(131 pages)
Specifications of MT47H256M4BT-5E:A TR
Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (256M x 4)
Speed
5ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
92-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557-1206-1
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Input Slew Rate Derating
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
For all input signals, the total
by adding the data sheet
value, respectively. Example:
t
crossing of V
a falling signal is defined as the slew rate between the last crossing of V
first crossing of V
If the actual signal is always earlier than the nominal slew rate line between shaded
“V
(page 58)).
If the actual signal is later than the nominal slew rate line anywhere between the sha-
ded “V
AC level to DC level is used for the derating value (see Figure 24 (page 58)).
t
crossing of V
ing signal, is defined as the slew rate between the last crossing of V
crossing of V
If the actual signal is always later than the nominal slew rate line between shaded “DC
to V
(page 59)).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded
“DC to V
level to V
Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached V
input signal is still required to complete the transition and reach V
For slew rates in between the values listed in Table 28 (page 56) and Table 29
(page 57), the derating values may obtained by linear interpolation.
IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last
IH, the nominal slew rate for a rising signal, is defined as the slew rate between the last
REF(DC)
REF(DC)
REF(DC)
REF(DC)
REF(DC)
to AC region,” use the nominal slew rate for the derating value (Figure 23
region,” use the nominal slew rate for the derating value (Figure 25
REF(DC)
IL(DC)max
REF(DC)
to AC region,” the slew rate of a tangent line to the actual signal from the
region,” the slew rate of a tangent line to the actual signal from the DC
level is used for the derating value (Figure 26 (page 59)).
IL(AC)max
.
and the first crossing of V
and the first crossing of V
IH[AC]
t
.
IS (base) and
/V
t
55
t
IS (total setup time) =
IS (setup time) and
IL[AC]
at the time of the rising clock transition), a valid
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
IH (base) value to the Δ
IH(AC)min
1Gb: x4, x8, x16 DDR2 SDRAM
REF(DC)
t
IH (hold time) required is calculated
t
IS (base) + Δ
Input Slew Rate Derating
. Setup nominal slew rate (
.
t
IH, nominal slew rate for a fall-
© 2004 Micron Technology, Inc. All rights reserved.
t
IS and Δ
t
IS.
IH(AC)
IH(DC)min
REF(DC)
/V
t
IH derating
IL(AC)
and the first
and the
.
t
IS) for
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