IS42S16400D-7T ISSI, Integrated Silicon Solution Inc, IS42S16400D-7T Datasheet - Page 35
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IS42S16400D-7T
Manufacturer Part Number
IS42S16400D-7T
Description
IC SDRAM 64MBIT 143MHZ 54TSOP
Manufacturer
ISSI, Integrated Silicon Solution Inc
Datasheet
1.IS42S16400D-7TL.pdf
(57 pages)
Specifications of IS42S16400D-7T
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (4M x 16)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
54-TSOP II
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IS42S16400D-7TL
Manufacturer:
ISSI
Quantity:
1 000
Company:
Part Number:
IS42S16400D-7TL
Manufacturer:
ISSI
Quantity:
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Part Number:
IS42S16400D-7TL
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Quantity:
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Part Number:
IS42S16400D-7TLI
Manufacturer:
ISSI
Quantity:
20 000
Fig CAP 3 - WRITE With Auto Precharge interrupted by a READ
IS42S16400D
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
Fig CAP 4 - WRITE With Auto Precharge interrupted by a WRITE
Integrated Silicon Solution, Inc. — www.issi.com
Rev. E
11/21/07
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing CAS latency later.
The PRECHARGE to bank n will begin after t
where t
The last valid WRITE to bank n will be data-in registered
one clock prior to the READ to bank m.
Internal States
COMMAND
ADDRESS
Internal States
COMMAND
ADDRESS
BANK m
WR
BANK n
BANK m
BANK n
begins when the READ to bank m is registered.
CLK
CLK
DQ
DQ
Page Active
T0
NOP
Page Active
T0
NOP
WRITE - AP
BANK n,
BANK n
WRITE - AP
T1
COL a
BANK n,
D
BANK n
Page Active
T1
COL a
D
IN
WRITE with Burst of 4
IN
a
a
Page Active
WRITE with Burst of 4
T2
D
NOP
D
T2
IN
NOP
IN
a+1
WR
a+1
is met,
READ - AP
BANK m,
BANK m
T3
COL b
T3
D
NOP
Interrupt Burst, Write-Back
IN
a+2
t
CAS Latency - 3 (BANK m)
WR
4. Interrupted by a WRITE (with or without auto precharge):
- BANK n
AWRITE to bank m will interrupt a WRITE on bank n when
registered. The PRECHARGE to bank n will begin after
t
m is registered. The last valid data WRITE to bank n will
be data registered one clock prior to a WRITE to bank m.
WR
T4
WRITE - AP
NOP
BANK m,
BANK m
T4
COL b
D
READ with Burst of 4
is met, where t
Interrupt Burst, Write-Back
IN
b
t
WR
WRITE with Burst of 4
- BANK n
T5
NOP
T5
D
NOP
IN
b+1
WR
begins when the WRITE to bank
T6
NOP
T6
D
D
NOP
Precharge
IN
t
OUT
RP - BANK n
b+2
b
t
Precharge
RP - BANK n
DON'T CARE
DON'T CARE
T7
NOP
D
T7
D
NOP
Precharge
OUT
Write-Back
IN
t
RP - BANK m
b+3
t
b+1
RP - BANK m
35