IS93C66A-2GRI ISSI, Integrated Silicon Solution Inc, IS93C66A-2GRI Datasheet - Page 3

• Manufacturer Part Number: IS93C66A-2GRI
• Description: IC EEPROM 4KBIT 3MHZ 8SOIC
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS93C66A-2GRI

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 1MHz, 2MHz, 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IS93C56A
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
08/15/07
Write Enable (WEN)
The write enable (WEN) instruction must be executed
before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done. When Vcc is applied,
this device powers up in the write disabled state. The
device then remains in a write disabled state until a WEN
instruction is executed. Thereafter, the device remains
enabled until a WDS instruction is executed or until Vcc
is removed. (See Figure 4.) (Note: Chip select must
remain LOW until Vcc reaches its operational value.)
Write (WRITE)
The WRITE instruction includes 8 or 16 bits of data to be
written into the specified register. After the last data bit
has been applied to D
of SK, CS must be brought LOW. If the device is write-
enabled, then the falling edge of CS initiates the self-
timed programming cycle (see WEN).
If CS is brought HIGH, after a minimum wait of 200 ns (5V
operation) after the falling edge of CS (t
indicate the READY/BUSY status of the chip. Logical “0”
means programming is still in progress; logical “1” means
the selected register has been written, and the part is
ready for another instruction (see Figure 5). The READY/
BUSY status will not be available if: a) The CS input goes
HIGH after the end of the self-timed programming cycle,
t
SK goes HIGH, which clears the status flag.
WP
; or b) Simultaneously CS is HIGH, Din is HIGH, and
IN
IS93C66A
, and before the next rising edge
CS
) D
OUT
will
Write All (WRALL)
The write all (WRALL) instruction programs all registers
with the data pattern specified in the instruction. As with the
WRITE instruction, the falling edge of CS must occur to
initiate the self-timed programming cycle. If CS is then
brought HIGH after a minimum wait of 200 ns (t
pin indicates the READY/BUSY status of the chip (see
Figure 6). Vcc is required to be above 4.5V for WRALL to
function properly.
Write Disable (WDS)
The write disable (WDS) instruction disables all programming
capabilities. This protects the entire device against acci-
dental modification of data until a WEN instruction is
executed. (When Vcc is applied, this part powers up in the
write disabled state.) To protect data, a WDS instruction
should be executed upon completion of each programming
operation.
Erase Register (ERASE)
After the erase instruction is entered, CS must be brought
LOW. The falling edge of CS initiates the self-timed internal
programming cycle. Bringing CS HIGH after a minimum of
t
chip: a logical “0” indicates programming is still in progress;
a logical “1” indicates the erase cycle is complete and the
part is ready for another instruction (see Figure 8).
Erase All (ERAL)
Full chip erase is provided for ease of programming. Erasing
the entire chip involves setting all bits in the entire memory
array to a logical “1” (see Figure 9). Vcc is required to be
above 4.5V for ERALL to function properly.
CS
, will cause D
OUT
to indicate the READ/BUSY status of the
CS
), the D
OUT
3