IS93C66A-2GRI-TR ISSI, Integrated Silicon Solution Inc, IS93C66A-2GRI-TR Datasheet - Page 2

• Manufacturer Part Number: IS93C66A-2GRI-TR
• Description: IC EEPROM 4KBIT 3MHZ 8SOIC
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS93C66A-2GRI-TR

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8 or 256 x 16)
• Speed: 1MHz, 2MHz, 3MHz
• Interface: Microwire, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN CONFIGURATIONS
IS93C56A
PIN DESCRIPTIONS
2
Applications
The IS93C56A/66A are very popular in many
applications which require low-power, low-density
storage. Applications using these devices include
industrial controls, networking, and numerous other
consumer electronics.
Endurance and Data Retention
The IS93C56A/66A are designed for applications requiring
up to 1M programming cycles (WRITE, WRALL, ERASE
and ERAL). They provide 40 years of secure data retention
without power after the execution of 1M programming cycles.
Device Operations
The IS93C56A/66A are controlled by a set of
instructions which are clocked-in serially on the Din pin.
Before each low-to-high transition of the clock (SK), the
CS pin must have already been raised to HIGH, and the
Din value must be stable at either LOW or HIGH. Each
8-Pin DIP, 8-Pin TSSOP
D
CS
SK
D
D
ORG
NC
Vcc
GND
OUT
D
CS
SK
OUT
IN
IN
1
2
3
4
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Organization Select
Not Connected
Power
Ground
8
7
6
5
VCC
NC
ORG
GND
IS93C66A
8-Pin JEDEC SOIC “GR”
D
OUT
D
CS
SK
IN
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
8-pad DFN
instruction begins with a start bit of the logical “1” or
HIGH. Following this are the opcode (2 bits),
address field (8 or 9 bits), and data, if appropriate. The
clock signal may be held stable at any moment to
suspend the device at its last state, allowing clock-
speed flexibility. Upon completion of bus
communication, CS would be pulled LOW. The device
then would enter Standby mode if no internal
programming is underway.
Read (READ)
The READ instruction is the only instruction that outputs
serial data on the D
address have been decoded, data is transferred from the
selected memory register into a serial shift register. (Please
note that one logical “0” bit precedes the actual 8 or 16-bit
output data string.) The output on D
low-to-high transitions of SK (see Figure 3).
Low Voltage Read
The IS93C56A/66A are designed to ensure that data read
operations are reliable in low voltage environments. They
provide accurate operation with Vcc as low as 1.8V.
Auto Increment Read Operations
In the interest of memory transfer operation applications,
the IS93C56A/66A are designed to output a continuous
stream of memory content in response to a single read
operation instruction. To utilize this function, the system
asserts a read instruction specifying a start location ad-
dress. Once the 8 or 16 bits of the addressed register have
been clocked out, the data in consecutively higher address
locations is output. The address will wrap around continu-
ously with CS HIGH until the chip select (CS) control pin is
brought LOW. This allows for single instruction data dumps
to be executed with a minimum of firmware overhead.
D
OUT
D
CS
SK
IN
(Top View)
Integrated Silicon Solution, Inc. — www.issi.com
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
OUT
pin. After the read instruction and
8-Pin JEDEC SOIC “G”
VCC
NC
CS
SK
OUT
(Rotated)
1
2
3
4
changes during the
8
7
6
5
ORG
GND
D
D
08/15/07
OUT
IN
Rev. D