MT48H16M16LFBF-75 AT:G TR Micron Technology Inc, MT48H16M16LFBF-75 AT:G TR Datasheet - Page 75

• Manufacturer Part Number: MT48H16M16LFBF-75 AT:G TR
• Description: IC SDRAM 256MBIT 132MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H16M16LFBF-75 AT:G TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (16Mx16)
• Speed: 132MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1245-2

Revision History
Rev. G, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 06/09
Rev. F, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 04/07
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
• Table 10, “DC Electrical Characteristics and Operating Conditions,” on page 45:
• Changed wording in Note 1 in the “Options” section on page 1.
• Changed CL = 2, -75 and -8 access times from “6ns” and “7ns” to “9ns” in Table 2 on
• Added “Revision :G” to Figure 1 on page 5.
• Changed refresh counter from “12” to “13” and changed Bank0 Memory Array from
• Changed E2, K2 to “DNU” and added the following sentence in the: “TEST pin must
• Added the following sentence to the “Input/output mask” description in Table 3 on
• Removed all the text after the first sentence in the “Initialization” section on page 12.
• Removed the first seven words in the “Mode Register” section on page 13.
• Removed “(sequential or interleaved)” and “...the specified time...” in the
• Changed “M13” and “M12” to “M13” and “M14” and deleted a column in the
• Removed the notes under Table 4 on page 15.
• Corrected the “Operating Mode” table in Figure 6 on page 14.
• Removed the following text under the “Operating Mode” section on page 16: “or test
• Removed “(nonburst)” under the “Write Burst Mode” section on page 16.
• Removed the last two sentences in the first paragraph and removed
• Changed the “Low-Power Extended Mode Register (EMR) Definition” heading to
• Moved Figure 7 to page 16.
• Changed the title of Figure 7 on page 16 to “EMR Definition.”
• Removed all bank address references from the “PASR Self-Refresh Coverage” in
• Replace the “Temperature-Compensated Self Refresh (TCSR)” section on page 17.
• Removed the second sentence in the “Partial Array Self-Refresh” section on page 18.
• Replaced Table 5 on page 19 and all the associated notes.
• Removed last paragraph and added “A0–A12” in the first sentence in the “Load Mode
• Removed “...and the DQ balls tri-state” from the “COMMAND INHIBIT” section on
• Moved the “Auto Precharge” section to page 21.
• Added a second paragraph in the “Deep Power Down” section on page 22.
• Added “BL = 2” to the note under Figure 20 on page 31.
• Added “BL = 2” to the note under Figure 22 on page 32.
• Changed “(see Figure 23)” to “(see Figure 25)” on page 34.
Updated I
page 1.
“8,192” to “4,096” in Figure 3 on page 7.
be tied to VssQ in normal operation” in Table 3 on page 10.
page 10: “DQM loading is designed to match that of DQ balls.”
“Mode Register” section on page 13.
“Operating Mode” table in Figure 3 on page 7.
modes” and “The programmed BL applies to both READ and WRITE bursts.”
“(BA1=1, AB0=0),” in the second paragraph in the “Low-Power Extended Mode Regis-
ter (EMR) Definition” section on page 16.
“Extended Mode Register (EMR)” on page 16.
Figure 7 on page 16.
Register” section on page 20.
page 19.
OZ
specification.
75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
©2006 Micron Technology, Inc. All rights reserved.
Revision History