IS24C128B-2ZLI ISSI, Integrated Silicon Solution Inc, IS24C128B-2ZLI Datasheet
IS24C128B-2ZLI
Specifications of IS24C128B-2ZLI
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IS24C128B-2ZLI Summary of contents
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... IS24C128B 2-WIRE (I SERIAL EEPROM Intregrated Silicon Solution, Inc. - www.issi.com Rev. 00F 09/18/09 IS24C128B 128K-bit ...
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... IS24C128B TABLE OF COnTEnTS Features ……………………………………………………….……………............3 Description ………………………………………………...………………............3 Functional Block Diagram … ...
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... SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C128B has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus. PRELIMInARY InFORMATIOn ...
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... IS24C128B FUNCTIONAL BLOCK DIAGRAM Vcc SDA SCL WP SLAVE ADDRESS REGISTER & COMPARATOR GND nMOS 4 CONTROL LOGIC WORD ADDRESS COUNTER ACK Clock DI/O Integrated Silicon Solution, Inc. — www.issi.com HIGH VOLTAGE GENERATOR, TIMING & CONTROL EEPROM ARRAY Y DECODER > DATA REGISTER Rev. 00F ...
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... IS24C128B PIN CONFIGURATION 8-Pin SOIC, TSSOP GND 4 5 PIn DESCRIPTIOnS A0-A2 Address Inputs SDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply GND Ground SCL This input clock pin is used to synchronize the data transfer to and from the device. ...
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... Start Condition The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The IS24C128B monitors the SDA and SCL lines and will not respond until the Start condition is met. Stop Condition The Stop condition is defined as a Low to High transition of SDA when SCL is High ...
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... IS24C128B acknowledges the word address, the Master device resends the Start condition and the Slave address, this time with the R/W bit set to one. The IS24C128B then responds with its ACK and sends the data requested. The Master device does not send an ACK but will generate a Stop condition ...
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... Figure 1. Typical System Bus Configuration SDA SCL Figure 2. Output Acknowledge SCL from Master Data Output from Transmitter Data Output from Receiver Figure 3. Start and Stop Conditions SCL SDA 8 Vcc Master IS24C128B Transmitter/ Receiver Integrated Silicon Solution, Inc. — www.issi.com ACK Rev. 00F 09/18/09 ...
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... IS24C128B Figure 4. Data Validity Protocol SCL SDA Figure 5. Slave Address BIT Figure 6. Byte Write Device R Address T SDA Bus Activity Figure 7. Page Write Device R T Word Address (n) Address T E SDA A Bus Activity R/W Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 ...
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... IS24C128B Figure 8. Current Address Read Activity Figure 9. Random Address Read Device R T Address T E SDA A Bus C Activity R/W DUMMY WRITE Figure 10. Sequential Read R E Device A Address D SDA A Bus C K Activity R Device A T Address D Data SDA A Bus R/W Word Word Address (n) Address (n) ...
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... IS24C128B Figure 11 DEEP SLEEP EnTRY/EXIT InITIATIOn Device R Address T SDA Bus Activity The slave does not provide an acknowledgement if the Deep Sleep Mode is enabled, and after stop, it begins to exit. Figure 12 DEEP SLEEP VERIFICATIOn * The slave does not provide an acknowledgement if the Deep Sleep Mode is already enabled. ...
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... IS24C128B ABSOLUTE MAXIMUM RATInGS Symbol Parameter V Supply Voltage s V Voltage on Any Pin p T Temperature Under Bias bias T Storage Temperature sTg i Output Current ouT notes: 1. Stresses violating the conditions listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only. Functional operation of the device outside these conditions or those indicated in the operational sections of this specification is not implied ...
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... IS24C128B AC ELECTRICAL CHARACTERISTICS Industrial ( Symbol Parameter (2) f SCL Clock Frequency SCL T Noise Suppression Time (1) t Clock Low Period Low t Clock High Period High t Bus Free Time Before New Transmission BUF t Start Condition Setup Time SU:STA t Stop Condition Setup Time SU:STO t Start Condition Hold Time ...
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... IS24C128B AC WAVEFORMS Figure 13. Bus Timing SCL t SU:STA SDA IN SDA OUT WP Figure 14. Write Cycle Timing SCL SDA 8th BIT WORD HIGH LOW t HD:DAT t t HD:STA SU:DAT ACK t WR STOP Condition Integrated Silicon Solution, Inc. — www.issi.com t SU:STO t BUF t SU:WP t HD:WP START Condition Rev ...
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... Voltage Range Part number* 1.8V to 5.5V IS24C128B-2GLI-TR IS24C128B-2ZLI- Contact ISSI Sales Representatives for availability and other package information. 2. The listed part numbers are packed in tape and reel “-TR” (4K per reel). UDFN/DFN is 5K per reel. 3. For tube/bulk packaging, if available, remove “-TR” at the end of the P/N. ...
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... IS24C128B 16 Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 ...
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... IS24C128B Integrated Silicon Solution, Inc. — www.issi.com Rev. 00F 09/18/09 17 ...