MT41J512M4JE-15E:A Micron Technology Inc, MT41J512M4JE-15E:A Datasheet - Page 167

• Manufacturer Part Number: MT41J512M4JE-15E:A
• Description: IC DDR3 SDRAM 2GBIT 82FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR3 SDRAMr

Specifications of MT41J512M4JE-15E:A

• Format - Memory: RAM
• Memory Type: DDR3 SDRAM
• Memory Size: 2G (512M x 4)
• Speed: 667MHz
• Interface: Parallel
• Voltage - Supply: 1.425 V ~ 1.575 V
• Operating Temperature: 0°C ~ 95°C
• Package / Case: 82-FBGA
• Organization: 512Mx4
• Address Bus: 18b
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 285mA
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 111: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Figure 112: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
PDF: 09005aef826aaadc/Source: 09005aef82a357c3
DDR3_D5.fm - Rev G 2/09 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
ODT
CK#
ODT
DQ
CK#
R
CK
DQ
R
CK
TT
TT
NOP
NOP
T0
T0
Notes:
Notes:
WRS4
Valid
WRS4
Valid
T1
T1
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
1. Via MRS or OTF. AL = 0, CWL = 5. R
2. In this example ODTH4 = 4 is satisfied exactly.
NOP
NOP
T2
T2
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
ODT can remain HIGH. R
ODTL
ODTL on
ODTL
ODTL on
CNW
CNW
ODTH4
NOP
ODTH4
NOP
T3
T3
WL
WL
NOP
NOP
T4
T4
ODTL
ODTL
t AON (MIN)
t AON (MIN)
CWN
CWN
t ADC (MAX)
TT
t ADC (MAX)
NOP
_
4
4
NOP
T5
T5
WR
167
is enabled.
TT
TT
R
R
NOP
NOP
TT
TT
T6
R
_
T6
_
DI
DI
n
n
_
_
TT
NOM
NOM
WR
WR
ODTL off
_
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR
n + 1
n + 1
DI
DI
and R
can be either enabled or disabled. If disabled,
NOP
NOP
n + 2
n + 2
T7
T7
DI
DI
TT
2Gb: x4, x8, x16 DDR3 SDRAM
n + 3
_
n + 3
DI
DI
WR
NOP
NOP
are enabled.
T8
T8
On-Die Termination (ODT)
ODTL off
t ADC (MIN)
t ADC (MAX)
t AOF (MIN)
t AOF (MAX)
NOP
NOP
©2006 Micron Technology, Inc. All rights reserved.
T9
T9
Transitioning
Transitioning
R
TT
_
NOM
NOP
T10
NOP
T10
t AOF (MIN)
t AOF (MAX)
Don’t Care
NOP
Don’t Care
T11
NOP
T11