CY7C1329-100AC Cypress Semiconductor Corp, CY7C1329-100AC Datasheet
CY7C1329-100AC
Specifications of CY7C1329-100AC
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CY7C1329-100AC Summary of contents
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... JEDEC-standard 100-lead TQFP pinout • “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. All synchronous inputs pass through input registers controlled by the rising edge of the clock ...
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... DDQ V SSQ BYTE3 SSQ V DDQ Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Document #: 38-05279 Rev. *A 100-pin TQFP CY7C1329 7C1329-133 4.2 Commercial 325 Commercial 5 CY7C1329 DDQ V 76 SSQ BYTE1 SSQ V 70 DDQ DDQ 60 V SSQ BYTE0 DQ 57 ...
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... Ground for the I/O circuitry. Should be connected to ground of the system. Selects burst order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and DDQ should remain static during device operation. No Connects. CY7C1329 , CE , and 1 2 are also loaded [1:0] is deasserted HIGH ...
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... Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A Synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1329 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ drivers safety precaution, DQ three-stated whenever a Write cycle is detected, regardless of the state of OE ...
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... The device must be deselected prior to entering 00 the “sleep” mode remain inactive for the duration of t returns LOW. 10 Test Conditions Min. ZZ > > < 0. ADSP CY7C1329 , ADSP, and ADSC must after the ZZ input ZZREC Max CYC CYC ADSC ADV Unit Write Hi-Z X ...
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... A Document #: 38-05279 Rev BWE Input Voltage Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) 65°C to +150°C Latch-up Current..................................................... >200 mA 55°C to +125°C Operating Range 0.5V to +4.6V Range 0. 0.5V Commercial DDQ CY7C1329 ...
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... MHz > V – 0. DDQ 10-ns cycle, 100 MHz 1/t MAX CYC Max Device Deselected Test Conditions MHz 3.3V 3.3V DDQ CY7C1329 Min. Max. Unit 3.135 3.6 V 3.135 3.6 V 2.4 V 0.4 V 2.0 V 0.3V V DDQ –0.3 0 – – 325 ...
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... EOHZ EOLZ CHZ CLZ CY7C1329 [10] ALL INPUT PULSES 3.3V 90% 10% GND < 3.3 ns (c) -133 -100 -75 Max. Min. Max. Min. 10 13.3 3.2 5.0 3.2 5 ...
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... GW to define a Write cycle (see Write Cycle Descriptions table). [3:0] 15. WDx stands for Write Data to Address X. Document #: 38-05279 Rev. *A Burst Write ADSP ignored with WD2 masks ADSP UNDEFINED = DON’T CARE CY7C1329 Pipelined Write Unselected inactive ADSC initiated Write WD3 Unselected with CE 2 High Page ...
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... RDx stands for Read Data from Address X. Document #: 38-05279 Rev. *A Burst Read ADSP ignored with Suspend Burst ADH RD2 OEHZ t DOH CLZ = DON’T CARE = UNDEFINED CY7C1329 Unselected Pipelined Read inactive 1 ADSC initiated Read RD3 masks ADSP Unselected with CHZ 2 Page ...
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... Data bus is driven by SRAM, but data is not guaranteed. Document #: 38-05279 Rev. *A Single Write Burst Read ADSP ignored with ADH RD3 masks ADSP OEHZ t DS See Note Out Out In = DON’T CARE = UNDEFINED CY7C1329 Unselected Pipelined Read inactive DOH Out Out Out Out T CHZ Page ...
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... CE is the combination of CE and CE . All chip selects need to be active in order to select the device Document #: 38-05279 Rev CYC CH WD1 t ADH t WES ADSP ignored with CE HIGH Out Out In = UNDEFINED = DON’T CARE CY7C1329 t CL WD2 WD3 WD4 t CEH t WEH D( DOH t CHZ Page ...
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... CE 1 LOW CE 2 HIGH I/Os Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05279 Rev ZZS I (active DDZZ Three-state CY7C1329 t ZZREC Page ...
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... Ordering Code 133 CY7C1329-133AC 100 CY7C1329-100AC Package Diagram 100-lead Thin Plastic Quad Flatpack ( 1.4 mm) A101 i486 is a trademark of Intel Corporation. Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. ...
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... Document Title: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM Document Number:38-05279 REV. ECN NO Issue Date ** 114388 03/25/02 *A 114499 04/11/02 Document #: 38-05279 Rev. *A Orig. of Description of changes Change DSG Change from Spec number: 38-00561 to 38-05279 GLC Changed to 1.5 set-up CY7C1329 Page ...