CY7C008-20AC Cypress Semiconductor Corp, CY7C008-20AC Datasheet
CY7C008-20AC
Specifications of CY7C008-20AC
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CY7C008-20AC Summary of contents
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... Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 64K x 8 organization (CY7C008) • 128K x 8 organization (CY7C009) • 64K x 9 organization (CY7C018) • 128K x 9 organization (CY7C019) • 0.35-micron CMOS for optimum speed/power [1] • ...
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... Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008/009 and CY7C018/019 are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. 100-Pin TQFP (Top View) ...
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... CY7C019 (128K x 9) CY7C018 (64K CY7C008/009 CY7C018/019 CY7C008/009 CY7C018/019 A7R 72 A8R 71 A9R 70 A10R 69 A11R 68 A12R 67 A13R 66 A14R 65 A15R 64 A16R 63 GND CE0R 57 CE1R 56 SEMR 55 R/WR 54 OER 53 GND 52 GND CY7C008/009 CY7C008/009 CY7C018/019 CY7C018/019 [1] -12 - 195 190 55 50 0.05 0.05 [6] -20 20 180 45 0.05 Page ...
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... Semaphore Enable Interrupt Flag Busy Flag Master or Slave Select Power Ground No Connect DC Input Voltage Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >1100V Latch-Up Current.................................................... >200 mA Operating Range Range Commercial Industrial CY7C008/009 CY7C018/019 Description V and –A for 128K devices –I/O for x8 devices and I/O – ...
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... Com’ [8] Ind. Com’l. 125 205 [8] Ind. Com’l. 0.05 0.5 [8] Ind. Com’l. 115 185 [8] Ind. [9] CY7C008/009 CY7C018/019 CY7C008/009 CY7C018/019 -15 -20 Min. Typ. Max. Min. Typ. 2.4 2.4 0.4 2.2 2.2 0.8 –10 10 –10 190 280 180 305 50 70 ...
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... Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 10% GND 3 ns [11] 1.00 0.90 0.80 0.70 = 1.4V 0.60 TH 0.50 0.40 0.30 0.20 0.10 0. CY7C008/009 CY7C018/019 Max OUTPUT 1.4V TH (c) Three-State Delay (Load 2) (Used for including scope and jig) 90% 10 Capacitance (pF) (b) Load Derating Curve ...
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... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document #: 38-06041 Rev. *A [12] CY7C008/009 CY7C018/019 [1] -12 -15 Min. Max. Min. Max time. SCE is less than t and t is less than t HZCE LZCE HZOE LZOE CY7C008/009 CY7C018/019 -20 Min. Max. Unit Page ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C008/009 and CY7C018/019 are designed with bat- tery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, with- ...
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... To access RAM SEM = access semaphore Document #: 38-06041 Rev. *A [21, 22, 23 [21, 24, 25] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads. , SEM = CY7C008/009 CY7C018/019 t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE Page ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document #: 38-06041 Rev. *A [26, 27, 28, 29 [29] t PWE [31] t HZWE t SD [26, 27, 28, 33 SCE LOW CE or SEM. PWE or (t PWE CY7C008/009 CY7C018/019 [31] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on HZWE SD . PWE Page ...
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... SPS Document #: 38-06041 Rev. *A [34 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [35, 36, 37] MATCH t SPS MATCH = CE = HIGH CY7C008/009 CY7C018/019 t t SAA OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE Page ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 38 LOW Document #: 38-06041 Rev. *A [38 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C008/009 CY7C018/019 BHA t BDD t DDD VALID t WDD Page ...
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... BUSY will be asserted. PS Document #: 38-06041 Rev. *A [39] ADDRESS MATCH BLC ADDRESS MATCH BLC [39 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C008/009 CY7C018/019 t BHC t BHC Page ...
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... Notes: 40. t depends on which enable pin ( depends on which enable pin (CE INS INR Document #: 38-06041 Rev [40 [41] t INR t WC [40 [41] [41] t INR ) is deasserted first R asserted last CY7C008/009 CY7C018/019 t RC READ FFFF (1FFFF for CY7C009/19 READ FFFE (1FFFE for CY7C009/19) Page ...
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... CY7C008/18, 1FFFF for the CY7C009/19) is the mailbox for the right port and the second-highest memory location (FFFE for the CY7C008/18, 1FFFE for the CY7C009/19) is the mail- box for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox ...
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... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C008/009 CY7C018/019 Operation [42] Right Port R 0R–16R ...
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... Ordering Information 64K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C008-12AC 15 CY7C008-15AC 20 CY7C008-20AC 128K x 8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C009-12AC 15 CY7C009-15AC 20 CY7C009-20AC CY7C009-20AI 64K x 9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C018-12AC 15 CY7C018-15AC 20 CY7C018-20AC 128K x 9 Asynchronous Dual-Port SRAM ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C008/009 CY7C018/019 ...
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... Document Title: CY7C008/009, CY7C018/019 64K/128K x 8/9 Dual Port Static RAM Document Number: 38-06041 Issue REV. ECN NO. Date ** 110189 09/29/01 *A 113542 04/15/02 Document #: 38-06041 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00665 to 38-06041 OOR Change pin 85 from BUSYL to BUSYR (pg. 3) ...