CY7C024-15AC Cypress Semiconductor Corp, CY7C024-15AC Datasheet
CY7C024-15AC
Specifications of CY7C024-15AC
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CY7C024-15AC Summary of contents
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... CY7C025/0251 to handle situations when multiple pro- cessors access the same piece of data. Two ports are provid- ed, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C024/0241 and CY7C025/0251 can be utilized as standalone 16-/18-bit du- al-port static RAMs or multiple devices can be combined in order to function as a 32-/36-bit or wider master/slave du- al-port static RAM ...
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... BUSY L (CY7C025/0251) A 12L A 11L A 0L R/W L SEM L INT L Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. I/O –I/O on the CY7C0241/0251 I/O –I/O on the CY7C0241/0251 Document #: 38-06035 Rev. ** I/O I/O CONTROL CONTROL MEMORY ADDRESS ARRAY DECODER INTERRUPT CE SEMAPHORE L ARBITRATION ...
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... Notes the CY7C025/0251. 12L the CY7C025/0251. 12R Document #: 38-06035 Rev. ** 84-Pin PLCC Top View CY7C024 100-Pin TQFP Top View CY7C024 CY7C024/0241 CY7C025/0251 INT L BUSY GND M/S 63 BUSY 62 R INT 7C024– INT 65 L BUSY 64 L GND 63 M/S ...
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... Top View CY7C0241/0251 Chip Enable Read/Write Enable Output Enable Address Data Bus Input/Output 15/17R Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground CY7C024/0241 CY7C025/0251 INT 65 L BUSY 64 L GND 63 M/S 62 BUSY 61 R INT ...
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... IN One Port CE or Com’ – 0.2V Ind V V – 0. 0.2V [7] Active Port Outputs MAX CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251– 170 160 40 30 Ambient Temperature + – + 7C024/0241–15 7C024/0241–25 7C025/0251–15 7C025/0251–25 Min. Typ. Max. Min. Typ. Max. ...
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... 250 TH OUTPUT C = 30pF (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% GND 3 ns CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251–55 Min. Typ. Max. Min. Typ. Max. Unit 2.4 2.4 0.4 2.2 2.2 –0.7 0.8 –0.7 –10 +10 – ...
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... Document #: 38-06035 Rev. ** [9] 7C024/0241–15 7C024/0241–25 7C025/0251–15 7C025/0251–25 Min. Max. Min. Max less than t and t HZCE LZCE HZOE CY7C024/0241 CY7C025/0251 7C024/0241–35 7C024/0241–55 7C025/0251–35 7C025/0251–55 Min. Max. Min. Max time. SCE is less than t . LZOE Page ...
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... BDD Data Retention Mode The CY7C024/0241 is designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. Chip enable (CE) must be held HIGH during data retention, with- ...
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... ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE and This waveform cannot be used for semaphore reads SEM = access semaphore CY7C024/0241 CY7C025/0251 t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE , SEM = 7C024–14 7C024–15 7C024–16 Page ...
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... AW [26] t PWE [29] t HZWE t SD [23, 24, 25, 31 SCE LOW CE or SEM and a LOW UB or LB. PWE PWE , SEM = CY7C024/0241 CY7C025/0251 [29] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed on HZWE SD 7C024–17 7C024–18 . PWE Page ...
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... SPS Document #: 38-06035 Rev. ** [32 SCE t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [33, 34, 35] MATCH t SPS MATCH = CE = HIGH CY7C024/0241 CY7C025/0251 OHA VALID ADRESS t ACE t SOP DATA VALID OUT t DOE READ CYCLE 7C024–19 7C024–20 Page ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 36 LOW Document #: 38-06035 Rev. ** [36 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C024/0241 CY7C025/0251 BHA t BDD t DDD VALID t WDD 7C024–21 7C024–22 Page ...
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... BUSY will be asserted. PS Document #: 38-06035 Rev. ** [37] ADDRESS MATCH BLC ADDRESS MATCH BLC [37 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C024/0241 CY7C025/0251 t BHC 7C024–23 t BHC 7C024–24 7C024–25 7C024–26 Page ...
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... R 39 depends on which enable pin (CE INS INR Document #: 38-06035 Rev [38 [39] t INR t WC [38 [39] [39] t INR ) is deasserted first R asserted last CY7C024/0241 CY7C025/0251 t RC READ FFF (1FFF CY7C025 READ FFE (1FFE CY7C025) Page 7C024–27 7C024–28 7C024–29 7C024–30 ...
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... When reading the device, the user must assert both the OE and CE pins. Data will be available t after ACE asserted. If the user of the CY7C024/0241 or CY7C025/0251 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing ...
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... Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C024/0241 CY7C025/0251 [3] I/O –I/O Operation 8 15 High Z Deselected: Power-Down High Z Deselected: Power-Down Data In Write to Upper Byte Only High Z Write to Lower Byte Only ...
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... CY7C024–15AC CY7C024–15JC 25 CY7C024–25AC CY7C024–25JC CY7C024–25AI CY7C024–25JI 35 CY7C024–35AC CY7C024–35JC CY7C024–35AI CY7C024–35JI 55 CY7C024–55AC CY7C024–55JC CY7C024–55AI CY7C024–55JI Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C025–15AC CY7C025–15JC CY7C025–15AI 25 CY7C025–25AC CY7C025– ...
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... Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C0241–15AC CY7C0241–15AI 25 CY7C0241–25AC CY7C0241–25AI 35 CY7C0241–35AC CY7C0241–35AI 55 CY7C0241–55AC CY7C0241–55AI Ordering Information (continued Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C0251–15AC 25 CY7C0251–25AC CY7C0251–25AI 35 CY7C0251–35AC CY7C0251–35AI 55 CY7C0251–55AC CY7C0251– ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Lead Plastic Leaded Chip Carrier J83 CY7C024/0241 CY7C025/0251 51-85048-A ...
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... Document Title: CY7C024/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06035 Issue REV. ECN NO. Date ** 110177 09/29/01 Document #: 38-06035 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00255 to 38-06035 CY7C024/0241 CY7C025/0251 ...