LH28F008SCT-L85 Sharp Microelectronics, LH28F008SCT-L85 Datasheet - Page 12

• Manufacturer Part Number: LH28F008SCT-L85
• Description: IC FLASH 8MBIT 85NS 40TSOP
• Manufacturer: Sharp Microelectronics

Specifications of LH28F008SCT-L85

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 85ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-TSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 425-1835; F008SCTL85; LHF08CH1

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3.5 Read Identifier Codes Operation
The read identifier codes operation outputs the
manufacturer
configuration codes for each block, and the master
lock configuration code (see Figure 4). Using the
manufacturer and device codes, the system CPU can
automatically match the device with its proper
algorithms.
configuration codes identify locked and unlocked
blocks and master lock-bit setting.
Figure 4. Device Identifier Code Memory Map
FFFFF
1FFFF
0FFFF
F0004
F0003
F0002
F0000
10004
10003
10002
10000
00004
00003
00002
00000
F0001
10001
00001
The
Block 15 Lock Configuration Code
Master Lock Configuration Code
Block 0 Lock Configuration Code
Block 1 Lock Configuration Code
code,
Future Implementation
Future Implementation
Future Implementation
Future Implementation
Future Implementation
block
(Blocks 2 through 14)
Manufacturer Code
Device Code
device
Reserved for
Reserved for
Reserved for
Reserved for
Reserved for
lock
code,
and
master
Block 15
block
Block 1
Block 0
lock
lock
LHF08CH1
3.6 Write
Writing commands to the CUI enable reading of
device data and identifier codes. They also control
inspection and clearing of the status register. When
V
erasure, byte write, and lock-bit configuration.
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Byte Write command requires the
command and address of the location to be written.
Set Master and Block Lock-Bit commands require the
command and address within the device (Master
Lock) or block within the device (Block Lock) to be
locked. The Clear Block Lock-Bits command requires
the command and address within the device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 16 and 17 illustrate
WE# and CE#-controlled write operations.
4 COMMAND DEFINITIONS
When the V
from the status register, identifier codes, or blocks
are enabled. Placing V
successful block erase, byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
PP
=V
PPH1/2/3
PP
, the CUI additionally controls block
voltage ≤ V
PPH1/2/3
PPLK
, Read operations
on V
PP
Rev. 1.3
enables
9