DSM2180F3-90T6 STMicroelectronics, DSM2180F3-90T6 Datasheet - Page 28

• Manufacturer Part Number: DSM2180F3-90T6
• Description: IC FLASH 1MBIT 90NS 52TQFP
• Manufacturer: STMicroelectronics

Specifications of DSM2180F3-90T6

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 5.5V
• Operating Supply Voltage (max): 4.5V
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1321

DSM2180F3
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. See application
note AN1171 for details on how to specify logic us-
ing PSDsoft Express.
As shown in Figure 15, the CPLD has the following
blocks:
■
■
■
■
■
Figure 15. Macrocell and I/O Port
Output Macrocell (OMC). Eight of the Output
Macrocells (OMC) are connected to Port B pins
and are named as McellAB0-McellAB7. The other
eight Macrocells are connected to Ports B or C
pins and are named as McellBC0-McellBC7.
OMCs may be used for internal feedback only
(buried registers), or their outputs may be routed
to external Port pins.
28/63
16 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
Product Term Allocator
AND Array capable of generating up to 130
product terms
Product Terms
from other
MacrocellS
PRODUCT TERM
PT
CLOCK
PT CLEAR
GLOBAL
CLOCK
CLOCK
SELECT
ALLOCATOR
PRODUCT TERMS
PT INPUT LATCH GATE/CLOCK
CPLD Macrocells
UP TO 10
POLARITY
SELECT
PT Output Enable ( OE )
Macrocell Feedback
I/O Port Input
PT PRESET
PR DI LD
D/T
CK
D/T/JK FF
SELECT
MCU DATA IN
CL
Q
MCU LOAD
DSP ADDRESS / DATA BUS
SELECT
COMB.
/REG
CONTROL
Macrocell
DATA
LOAD
Out to
MCU
Macrocell
■
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the device internal data
bus and can be directly accessed by the DSP. This
enables the DSP software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macro cell architectures.
The Output Macrocell (OMC) architecture is
shown in Figure 17. As shown in the figure, there
are native product terms available from the AND
Array, and borrowed product terms available (if
unused) from other Output Macrocells (OMC). The
polarity of the product term is controlled by the
XOR gate. The Output Macrocell (OMC) can im-
plement either sequential logic, using the flip-flop
I/O Port
Alloc.
to
Two I/O Ports.
OUTPUT
CPLD
DATA
CPLD OUTPUT
ADDRESS OUT
I/O PORTS
WR
WR
Input Macrocells
LATCHED
PDR
D
TO OTHER I/O PORTS
D
REG.
DIR
INPUT
Q
Q
MUX
SELECT
Q
Q D
D
G
AI04902B
I/O Pin