M58LW032D110N6 STMicroelectronics, M58LW032D110N6 Datasheet - Page 49

• Manufacturer Part Number: M58LW032D110N6
• Description: IC FLASH 32MBIT 110NS 56TSOP
• Manufacturer: STMicroelectronics

Specifications of M58LW032D110N6

• Format - Memory: FLASH
• Memory Type: FLASH - Nor
• Memory Size: 32M (4Mx8, 2Mx16)
• Speed: 110ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-TSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1725

REVISION HISTORY
Table 30. Document Revision History
04-Jun-2002
16-Jun-2002
06-Aug-2002
14-Oct-2002
16-Dec-2002
30-May-2003
12-Sep-2003
13-Aug-2004
Date
Version
-01
1.1
2.0
2.1
2.2
2.3
2.4
3.0
First Issue
Revision numbering modified: a minor revision will be indicated by incrementing the
digit after the dot, and a major revision, by incrementing the digit before the dot.
(revision version 01 becomes 1.0).
Figure 5.
Device Code changed, Word Effective Programming Time modified, V
modified (esp. in Tables
Block Erase and Program Write Buffer Time parameters modified in
90ns Speed Class added (Table 15, 16, 17, 18,
Figure 2., Logic
modified. Document status changed from Product Preview to Preliminary Data.
A0 Address Line described separately from others (A1-A21) in
“SIGNAL
Operations. Byte signal added to
t
t
Enable Controlled. “Write 70h” removed from flowchart Figures
3., Bus
Table 9., Program, Erase Times and Program Erase Endurance Cycles
Table 6., Read Electronic Signature
in
in
all CFI Tables. Block Protect setup command address modified in
4.,
information. I
clarified and I
parameter added to Reset, Power-Down and Power-Up AC Waveforms figure and
Characteristics table.
Summary Description clarified, Bus Operations clarified,
added, Status Register bit nomenclature modified, V
Flowcharts. Lead-free packing options added to
t
Chip Enable Controlled.
Full datasheet.
Lead-Free package options mentioned in
DESCRIPTION. T
TSOP56 and TBGA64 package specifications updated (see
Figure 15.
BLQV
ELLH
EHAX
Figure 4., TBGA64 Connections (Top view through
Table 24., Query Structure
Commands. Data and Descriptions clarified in CFI
removed from
and t
and t
Operations, clarified. REVISION HISTORY moved to after the appendices.
modified. t
DESCRIPTIONS” paragraph. Address Lines modified in
and
BLQZ
EHDX
OSC
DDO
Table
Diagram, modified. V
added to
minimum values modified in
parameter added to Absolute Maximum Ratings table. I
and V
LEAD
WHDX
Table 18., Write AC Characteristics, Chip Enable Controlled.
21.) Document moved to new template.
and note 1 added to
PENH
12
Table
and t
and 22, and V
parameters added to DC Characteristics table. t
Overview. Note regarding A0 value in x8 mode added to
WHAX
15., Bus Read AC Characteristics, timings t
Figure 9., Bus Read AC
Revision Details
clarified. Certain DU connections changed to NC
modified in
DD
, V
DDQ
FEATURES SUMMARY
DDQ
Table 11., Absolute Maximum
Table 18., Write AC Characteristics,
removed from note 1 below
, V
19
Ordering Information
Table 17.
SS
and
PEN
and V
package). x8 Address modified
Table 29., Extended Query
22
READ MODES
Invalid Error clarified in
Waveforms, timings t
modified accordingly).
SSQ
Figure
Table 1.
pin descriptions
17
Table
Table 3., Bus
and 19.
and
14.,
Table 9.
M58LW032D
Scheme.
DDQ
SUMMARY
and in
Table
modified.
section
DD
Table
range
Table
Ratings.
AVLH
and V
PHWL
20.,
ELBL
9.).
Chip
and
49/50
LKO
,