PSD813F1A-90J STMicroelectronics, PSD813F1A-90J Datasheet - Page 52

• Manufacturer Part Number: PSD813F1A-90J
• Description: IC FLASH 1MBIT 90NS 52PLCC
• Manufacturer: STMicroelectronics

Specifications of PSD813F1A-90J

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 1M (128K x 8)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-1975-5

PSD813F1A
I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP address space.
The topics discussed in this section are:
■
■
■
■
■
General Port Architecture
The general architecture of the I/O Port is shown
in
tures are shown in
32., page
port pin has been defined, that pin will no longer be
available for other purposes. Exceptions will be
noted.
As shown in
an output multiplexer whose selects are driven by
the configuration bits in the Control Registers
(Ports A and B only) and PSDsoft Express Config-
uration. Inputs to the multiplexer include the fol-
lowing:
■
■
■
■
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
PDB is connected to the Internal Data Bus for
feedback and can be read by the microcontroller.
The Data Out and Macrocell outputs, Direction
and Control Registers, and port pin input are all
connected to the PDB.
52/111
Figure 27., page
General Port architecture
Port Operating Modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port Functionality.
Output data from the Data Out Register
Latched address outputs
CPLD Macrocell output
External Chip Select from CPLD.
63. In general, once the purpose for a
Figure 27., page
Figure 29., page 60
53. Individual Port architec-
53, the ports contain
to
Figure
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND array enable product term
and the Direction Register. If the enable product
term of any of the array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the microcontroller. The PDB feedback path al-
lows the microcontroller to check the contents of
the registers.
Ports A, B, and C have embedded Input Macro-
cells (IMCs). The IMCs can be configured as latch-
es, registers, or direct inputs to the PLDs. The
latches and registers are clocked by the address
strobe (AS/ALE) or a product term from the PLD
AND array. The outputs from the IMCs drive the
PLD input bus and can be read by the microcon-
troller.
Macrocell, page
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the microcontroller writing to the Control
Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft Ex-
press must be programmed into the device and
cannot be changed unless the device is repro-
grammed. The modes that can be changed by the
microcontroller can be done so dynamically at run-
time. The PLD I/O, Data Port, Address Input, and
Peripheral I/O modes are the only modes that
must be defined before programming the device.
All other modes can be changed by the microcon-
troller at run-time.
Table 19., page 54
available on each port.
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following subsections.
See
42.
the
summarizes which modes are
section
Table 22., page 57
entitled
shows
Input