CY7C1360B-166AJC Cypress Semiconductor Corp, CY7C1360B-166AJC Datasheet - Page 25
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CY7C1360B-166AJC
Manufacturer Part Number
CY7C1360B-166AJC
Description
IC SRAM 9MBIT 166MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1360B-166AJC.pdf
(34 pages)
Specifications of CY7C1360B-166AJC
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Memory Size
9M (256K x 36)
Speed
166MHz
Interface
Parallel
Voltage - Supply
3.135 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
428-1503
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1360B-166AJCT
Manufacturer:
CYP
Quantity:
1 268
Document #: 38-05291 Rev. *C
Switching Characteristics
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Shaded areas contain advance information.
Notes:
16. Timing reference level is 1.5V when V
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; t
19. t
20. At any given voltage and temperature, t
21. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
CHZ
, t
CLZ
,t
OELZ
, and t
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid after CLK Rise
Data Output Hold after CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up before CLK Rise
ADSC , ADSP Set-up before CLK Rise
ADV Set-up before CLK Rise
GW, BWE, BW
Data Input Set-up before CLK Rise
Chip Enable Set-Up before CLK Rise
Address Hold after CLK Rise
ADSP , ADSC Hold after CLK Rise
ADV Hold after CLK Rise
GW , BWE , BW
Data Input Hold after CLK Rise
Chip Enable Hold after CLK Rise
DD
OEHZ
(Typical) to the First Access
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
X
[19, 20, 21]
X
Description
[19, 20, 21]
Hold after CLK Rise
DDQ
Set-up before CLK Rise
OEHZ
Over the Operating Range
= 3.3V and is 1.25V when V
POWER
is less than t
[19, 20, 21]
is the time that the power needs to be supplied above V
[19, 20, 21]
OELZ
[18]
and t
CHZ
DDQ
is less than t
[16, 17]
= 2.5V.
Min.
1.25
1.25
1.25
4.4
1.8
1.8
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
225 MHz
CLZ
to eliminate bus contention between SRAMs when sharing the same
Max
2.8
2.8
2.8
2.8
Min.
1.25
1.25
1.25
5.0
2.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
DD
1
0
200 MHz
(minimum) initially before a Read or Write operation
Max
3.0
3.0
3.0
3.0
Min.
1.25
1.25
1.25
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
166 MHz
CY7C1360B
CY7C1362B
Max
Page 25 of 34
3.5
3.5
3.5
3.5
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns