CY7C1382B-167AC Cypress Semiconductor Corp, CY7C1382B-167AC Datasheet

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... READ cycle. This device also in- corporates pipelined enable circuit for easy depth expansion without penalizing system performance. SRAMs integrate All inputs and outputs of the CY7C1380B and the CY7C1382B are JEDEC standard JESD8-5 compatible. 200 MHz 167 MHz 3 ...

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... Logic Block Diagram CY7C1380B - 512K x 36 CLK ADV ADSC ADSP A [18: BWE Logic Block Diagram CY7C1382B - CLK ADV ADSC ADSP A [19: BWE Document #: 38-05267 Rev. *A MODE [1;0] Q BURST 0 COUNTER CE Q CLR ADDRESS CE REGISTER BYTEWRITE REGISTERS BYTEWRITE REGISTERS BYTEWRITE REGISTERS BYTEWRITE REGISTERS ...

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... DQa DQb 58 23 DPb DQa DQa SSQ SSQ DDQ DDQ NC DQa 53 28 DQa DQPa CY7C1380B CY7C1382B DDQ V 76 SSQ NC 75 DPa 74 DQa 73 DQa SSQ V 70 DDQ DQa 69 DQa 68 CY7C1382B ( DQa 63 DQa DDQ V 60 SSQ DQa 59 DQa SSQ V 54 DDQ Page ...

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... A A ADSC DPc DQc DQc DQc BWc ADV BWb BWc DQc DQd V CLK DQd BWd NC BWa DQd V BWE DQd DPd MODE 64M TMS TDI TCK TDO CY7C1382B ( ADSP ADSC DQb DQb BWb ADV DQb V CLK BWa SS DQb V BWE DPb MODE V V ...

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... DPc DQc DQc V E DQc DQc V F DQc DQc V G DQc DQc DQd DQd V K DQd DQd V L DQd DQd V M DQd DQd V N DPd 64M R MODE 32M CY7C1382B ( FBGA DQb DQb DQb DQb DQb DQb DQb DQb DPb 64M ...

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... LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition.DQ a,b,c and d are 8 bits wide. DP a,b,c and d are 1 bit wide. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA Only) CY7C1380B CY7C1382B CE , and 1, 2 are also loaded [1:0] is deasserted HIGH ...

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... Power supply for the I/O circuitry. Should be connected to a 2.5 –5% –3.3V 10% power supply. Ground for the I/O circuitry. Should be connected to ground of the system. No connects. Reserved for address expansion. Pins are not internally connect- ed. No connects. Pins are not internally connected. CY7C1380B CY7C1382B Page ...

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... Asserting the Byte Write Enable input (BWE) with the selected Byte Write CY7C1382B) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. ...

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... The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of t ZZREC Test Conditions Min. ZZ > V – 0. > V – 0. < 0.2V 2t CYC CY7C1380B CY7C1382B Second Third Address Address A A [1:0] [1: after the ZZ input returns LOW ...

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... The DQ pins are controlled by the current cycle and the OE signal asynchronous and is not sampled with the clock and CE are available only in the TQFP package. BGA package has a single chip select Document #: 38-05267 Rev ADSP CY7C1380B CY7C1382B ADSC ADV ...

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... Write Bytes Write Bytes Write All Bytes Write All Bytes Function (1382) Read Read Write Byte and DP [7:0] 0 Write Byte and DP [15:8] 1 Write All Bytes Write All Bytes Document #: 38-05267 Rev BWE BWd BWE CY7C1380B CY7C1382B BWc BWb BWa BWb BWa Page ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380B/CY7C1382B incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port oper- ates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compli- ance ...

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... TDI and TDO pins. The advan- tage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1380B CY7C1382B Page ...

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... RESET 1 TEST-LOGIC/ 0 IDLE Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05267 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1380B CY7C1382B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...

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... TAP Controller [5, 6] Over the Operating Range Test Conditions 100 8 100 A OL GND DDQ /2, Undershoot:V (AC)<0.5V for t<t /2, Power-up TCYC CY7C1380B CY7C1382B 0 Selection Circuitry Min. Max. 2 0.2 DD 0.4 0.2 1.7 V 0.3 DD 0.5 0 <2.6V and V <2.4V and V <1.4V for t<200 ms. IH ...

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... Test conditions are specified using the load in TAP AC test conditions. TR/ ns. Document #: 38-05267 Rev. *A [7, 8] Over the Operating Range Description CY7C1380B CY7C1382B Min. Max Unit 100 ns 10 MHz 40 ns ...

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... TAP Timing and Test Conditions 1.25V 50 TDO GND (a) Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 38-05267 Rev. *A ALL INPUT PULSES 3.3V 1.50V TCYC t TMSS t TMSH t TDIS t TDIH t t TDOV TDOX CY7C1380B CY7C1382B Page ...

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... Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1380B CY7C1382B Description Reserved for version number Defines depth of SRAM. 512K or 1M Defines with of the SRAM. x36 or x18 ...

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... ADSC DQd DQd 1K 25 BWE DQd DQd 2N 27 CLK DQd MODE 3R 29 BWa BWb DQb CY7C1380B CY7C1382B Signal Bump Signal Name ID Bit # Name 2R 36 DQb 2T 37 DQb 3T 38 DQb DQb 3B 41 DQb 5B 42 DQb 7P 43 DQb 6N 44 DQb 6L 45 MODE ...

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... MHz MAX CYC 7.5-ns cycle, 133 MHz Max Device All speed grades DD Deselected, V < 0. > V – 0.3V DDQ CY7C1380B CY7C1382B Ambient [10] Temp 0°C to +70°C 3.3V 2.5V – 5% –5% / +10% 3.3V + 10% Min. Max. 3.135 3.63 2.375 3.63 2.4 2 ...

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... Test Conditions T 25° 1MHz 3.3V 3.3V DDQ [12] R=317 3.3V OUTPUT 5 pF R=351 R=351 INCLUDING JIG AND SCOPE (b) Symbol JA JC CY7C1380B CY7C1382B Min. Max. 110 100 Max ALL INPUT PULSES 3.0V 90% 90% 10% GND 1 V/ns (c) TQFP Typ. 25 Page Unit Unit 10% 1 V/ns ...

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... EOLZ CHZ CLZ CY7C1380B CY7C1382B -167 -150 -133 Max. Min. Max. Min. Max. 6.7 7.5 2.3 2.5 2.3 2.5 1.5 1.5 0.5 0.5 3.4 3.8 4 ...

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... WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Descriptions table). 17. WDx stands for Write Data to Address X. Document #: 38-05267 Rev. *A Burst Write ADSP ignored with WD2 masks ADSP UNDEFINED = DON’T CARE CY7C1380B CY7C1382B Pipelined Write Unselected inactive ADSC initiated write WD3 Unselected with CE 2 High Page ...

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... RDx stands for Read Data from Address X. Document #: 38-05267 Rev. *A Burst Read ADSP ignored with Suspend Burst ADH OEHZ t DOH CLZ = DON’T CARE = UNDEFINED CY7C1380B CY7C1382B Unselected Pipelined Read inactive 1 ADSC initiated read RD3 masks ADSP Unselected with CHZ 2 Page ...

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... EOV t CEH OE t EOLZ Data In/Out 1a Out t CO Document #: 38-05267 Rev. *A Single Write Burst Read ADSP ignored with ADH RD3 masks ADSP EOHZ Out In = DON’T CARE = UNDEFINED CY7C1380B CY7C1382B Unselected Pipelined Read inactive DOH Out Out Out Out t CHZ Page ...

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... CE is the combination of CE and CE . All chip selects need to be active in order to select the device Document #: 38-05267 Rev CYC CH WD1 t ADH t WES ADSP ignored with CE HIGH Out Out In = UNDEFINED = DON’T CARE CY7C1380B CY7C1382B t CL WD2 WD3 WD4 t CEH t WEH D( DOH t CHZ Page ...

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... Switching Waveforms (continued) OE Switching Waveforms OE I/Os Document #: 38-05267 Rev EOV t EOHZ Three-State t EOLZ CY7C1380B CY7C1382B Page ...

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... CE 2 HIGH I/Os NotefjdfdhfdjfdfjdjdjdjNo Note: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 22. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05267 Rev ZZS I (active DDZZ Three-state CY7C1380B CY7C1382B t ZZREC Page ...

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... Ordering Information Speed (MHz) Ordering Code 200 CY7C1380B-200AC 167 CY7C1380B-167AC 150 CY7C1380B-150AC 133 CY7C1380B-133AC 200 CY7C1382B-200AC 167 CY7C1382B-167AC 150 CY7C1382B-150AC 133 CY7C1382B-133AC 200 CY7C1380B-200BGC 167 CY7C1380B-167BGC 150 CY7C1380B-150BGC 133 CY7C1380B-133BGC 200 CY7C1382B-200BGC 167 CY7C1382B-167BGC 150 CY7C1382B-150BGC 133 CY7C1382B-133BGC 200 CY7C1380B-200BZC 167 ...

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... CY7C1382B-133BGI 167 CY7C1380B-167BZI 150 CY7C1380B-150BZI 133 CY7C1380B-133BZI 167 CY7C1382B-167BZI 150 CY7C1382B-150BZI 133 CY7C1382B-133BZI Shaded areas contain advance information. Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05267 Rev. *A ...

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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05267 Rev. *A CY7C1380B CY7C1382B 51-85050-A Page ...

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... Package Diagrams (continued) Document #: 38-05267 Rev. *A 165-Ball FBGA ( 1.2 mm) BB165A CY7C1380B CY7C1382B 51-85122-*B Page ...

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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead PBGA ( 2.4 mm) BG119 CY7C1380B CY7C1382B 51-85115-*A Page ...

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... Revision History Document Title: CY7C1380B, CY7C1382B 512K x 36M/ Pipelined SRAM Document Number: 38-05267 Issue REV. ECN NO. Date ** 114166 3/18/02 *A 114817 4/10/02 Document #: 38-05267 Rev. *A Orig. of Change DESCRIPTION OF CHANGE DSG Change from Spec number: 38-01074 to 38-05267 DSG Converted updated version: earlier version converted in Rev. **. ...