M25P40-VMN6TP NUMONYX, M25P40-VMN6TP Datasheet - Page 18
![IC FLASH 4MBIT 50MHZ 8SOIC](/photos/7/28/72827/m25p40-vmn6tp_sml.jpg)
M25P40-VMN6TP
Manufacturer Part Number
M25P40-VMN6TP
Description
IC FLASH 4MBIT 50MHZ 8SOIC
Manufacturer
NUMONYX
Series
Forté™r
Datasheet
1.M25P40-VMP6G.pdf
(61 pages)
Specifications of M25P40-VMN6TP
Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
50MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4544-2
497-4544-2
M25P40-VMN6TPTR
497-4544-2
M25P40-VMN6TPTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25P40-VMN6TP
Manufacturer:
MICRON
Quantity:
19 000
Company:
Part Number:
M25P40-VMN6TP
Manufacturer:
ST
Quantity:
6
Part Number:
M25P40-VMN6TP
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
M25P40-VMN6TPB
Manufacturer:
MICRON
Quantity:
21 000
Company:
Part Number:
M25P40-VMN6TPB
Manufacturer:
MICRON
Quantity:
11 200
Company:
Part Number:
M25P40-VMN6TPB
Manufacturer:
Numonyx
Quantity:
22 500
Part Number:
M25P40-VMN6TPB
Manufacturer:
MICRON
Quantity:
20 000
6
18/61
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S) must be driven High after the last bit of the instruction sequence has been
shifted in.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power-
down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
Table
4.