M93S66-WMN6T STMicroelectronics, M93S66-WMN6T Datasheet - Page 11
![IC EEPROM 4KBIT 2MHZ 8SOIC](/photos/1/38/13851/497-8-soic_sml.jpg)
M93S66-WMN6T
Manufacturer Part Number
M93S66-WMN6T
Description
IC EEPROM 4KBIT 2MHZ 8SOIC
Manufacturer
STMicroelectronics
Datasheet
1.M93S46-WMN6TP.pdf
(34 pages)
Specifications of M93S66-WMN6T
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
4K (256 x 16)
Speed
2MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M93S66-WMN6T
Manufacturer:
ST
Quantity:
20 000
Part Number:
M93S66-WMN6TP
Manufacturer:
ST
Quantity:
20 000
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (t
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
Write All
The Write All Memory with same Data (WRAL) in-
struction is valid only after the Protection Register
has been cleared by executing a Protection Reg-
ister Clear (PRCLEAR) instruction. The Write All
Memory with same Data (WRAL) instruction simul-
taneously writes the whole memory with the same
data word given in the instruction.
SLSH
) before the status information
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
be started, and the addressed location will not be
programmed.
While the M93Sx6 is performing a write cycle, but
after a delay (t
becomes available, Chip Select Input (S) can be
driven High to monitor the status of the write cycle:
Serial Data Output (Q) is driven Low while the
M93Sx6 is still busy, and High when the cycle is
complete, and the M93Sx6 is ready to receive a
new instruction. The M93Sx6 ignores any data on
the bus while it is busy on a write cycle. Once the
M93Sx6 is Ready, Serial Data Output (Q) is driven
High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought
Low.
Programming is internally self-timed, so the exter-
nal Serial Clock (C) may be disconnected or left
running after the start of a write cycle.
SLSH
M93S66, M93S56, M93S46
) before the status information
11/34