M95010-WMN6P STMicroelectronics, M95010-WMN6P Datasheet
M95010-WMN6P
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M95010-WMN6P
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M95010-WMN6P Summary of contents
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... Device summary Reference M95040 M95040 M95040-W M95040-R M95020 M95020 M95020-W M95020-R M95010 M95010 M95010-W M95010-R September 2009 Part number Doc ID 6512 Rev 8 M95040 M95020 M95010 with high-speed clock SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width UFDFPN8 (MB) 2 × 1/43 www.st.com 1 ...
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... Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Status Register (RDSR 6.3.1 6.3.2 2/ Operating supply voltage Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 6512 Rev 8 M95040, M95020, M95010 ...
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... M95040, M95020, M95010 6.3.3 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE Power-up and delivery states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11 Part numbering ...
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... UFDFPN8 (MLP8) — 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 25. Available M95010 products (package, voltage range, temperature grade Table 26. Available M95020 products (package, voltage range, temperature grade Table 27. Available M95040 products (package, voltage range, temperature grade Table 28 ...
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... M95040, M95020, M95010 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 ...
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... The M95040 Kbit (512 x 8) electrically erasable programmable memory (EEPROM), accessed by a high speed SPI-compatible bus. The other members of the family (M95020 and M95010) are identical, though proportionally smaller (2 and 1 Kbit, respectively). Each device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken low ...
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... M95040, M95020, M95010 Table 2. Signal names Signal name HOLD Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Doc ID 6512 Rev 8 Description 7/43 ...
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... Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low. 8/43 must be held stable and within the specified valid range: CC Table 13 to Table 16). These signals are described next. Doc ID 6512 Rev 8 M95040, M95020, M95010 , ...
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... M95040, M95020, M95010 2.6 Write Protect (W) This input signal is used to control whether the memory is write protected. When Write Protect (W) is held low, writes to the memory are disabled, but other operations remain enabled. Write Protect (W) must either be driven high or low, but must not be left floating. ...
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... V CC Table 9 and Table 10 and the rise time must not vary faster than 1 V/µs. Table 8, Table 9 Doc ID 6512 Rev 8 M95040, M95020, M95010 During this SS CC voltage via a suitable pull-up resistor (see CC operating voltage CC supply voltage below the minimum ...
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... M95040, M95020, M95010 3 Connecting to the SPI bus These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low ...
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... Stand-by mode and not transferring data: ● C remains at 0 for (CPOL=0, CPHA=0) ● C remains at 1 for (CPOL=1, CPHA=1) Figure 4. SPI modes supported CPOL CPHA 12/43 MSB Doc ID 6512 Rev 8 M95040, M95020, M95010 Figure 4, is the clock polarity when the MSB AI01438B ...
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... M95040, M95020, M95010 4 Operating features 4.1 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. ...
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... Protected array addresses Protected block M95040 none none Upper quarter 180h - 1FFh Upper half 100h - 1FFh Whole memory 000h - 1FFh Doc ID 6512 Rev 8 M95040, M95020, M95010 M95020 M95010 none none C0h - FFh 60h - 7Fh 80h - FFh 40h - 7Fh 00h - FFh 00h - 7Fh ...
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... M95040, M95020, M95010 5 Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD W Control Logic Address Register and Counter Figure 6. High Voltage Generator I/O Shift Register Data Register 1 Page X Decoder Doc ID 6512 Rev 8 Memory organization Status Register Size of the Read only ...
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... Read from Memory Array Write to Memory Array 7, to send this instruction to the device, Chip Select (S) is driven low Instruction D High Impedance Q Doc ID 6512 Rev 8 M95040, M95020, M95010 Table 4. Table 4), the device automatically Instruction Format (1) 0000 X110 (1) 0000 X100 (1) 0000 X101 (1) 0000 X001 0000 A ...
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... M95040, M95020, M95010 6.2 Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high ...
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... Table 5. Status register format 18/ send this instruction to the device, Chip Select (S) is first driven low. Table 3) becomes protected against Write 1 1 Doc ID 6512 Rev 8 M95040, M95020, M95010 BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit b0 WIP ...
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... M95040, M95020, M95010 Figure 9. Read Status Register (RDSR) sequence High Impedance Instruction Status Register Out MSB Doc ID 6512 Rev 8 Instructions Status Register Out MSB 7 AI01444D 19/43 ...
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... Write Protect (W) is low during the WRSR command (instruction, address and data) 20/43 to complete (as specified in W Figure 10 write cycle Instruction Register High Impedance MSB Doc ID 6512 Rev 8 M95040, M95020, M95010 Table 13 to Table 20). The Status AI01445B ...
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... M95040, M95020, M95010 6.5 Read from Memory Array (READ) As shown in Figure low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in register, and the byte of data at that address is shifted out, on Serial Data Output (Q) ...
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... Chip Select (S) is driven high after the eighth bit of the data byte is internally executed as a sequence of two consecutive Instruction Byte Address Table 6, the most significant address bits are Don’t Care. Doc ID 6512 Rev 8 M95040, M95020, M95010 Table 13 to Table 20). After this Figure 13, the next byte Data Byte AI01442D ...
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... M95040, M95020, M95010 Figure 13. Page Write (WRITE) sequence Depending on the memory size, as shown Instruction Byte Address Data Byte 2 Data Byte Table 6, the most significant address bits are Don’t Care. Doc ID 6512 Rev 8 Instructions Data Byte Data Byte AI01443D 23/43 ...
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... The BP1 and BP0 bits of the Status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array set at all 1s (FFh). The Block Protect (BP1 and BP0) bits are initialized to 0. 24/43 Doc ID 6512 Rev 8 M95040, M95020, M95010 ...
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... M95040, M95020, M95010 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Input rise and fall times Input pulse voltages Input and output timing reference voltages 1. Output Hi-Z is defined as the point where data out is no longer driven. 26/43 Parameter Parameter Parameter Parameter Doc ID 6512 Rev 8 M95040, M95020, M95010 Min. Max. Unit 4.5 5.5 V –40 125 °C Min ...
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... M95040, M95020, M95010 Figure 14. AC test measurement I/O waveform Table 12. Capacitance Symbol C Output capacitance (Q) OUT C Input capacitance (D) IN Input capacitance (other pins) 1. Sampled only, not 100% tested Table 13. DC characteristics (M950x0, device grade 3) Symbol Parameter I Input leakage current LI I Output leakage current ...
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... Internal reset threshold (1) V RES voltage 1. Characterized only, not 100% tested. 28/43 Test condition OUT 0.1V /0. MHz 2 open 2 1 –0 Doc ID 6512 Rev 8 M95040, M95020, M95010 Min. Max. Unit ± 2 µA ± 2 µ µA –0. 0 1.0 1.65 V ...
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... M95040, M95020, M95010 Table 15. DC characteristics (M950x0-W, device grade 3) Symbol I Input leakage current LI I Output leakage current LO I Supply current CC Supply current I CC1 (Standby Power mode) V Input low voltage IL V Input high voltage IH V Output low voltage OL V Output high voltage ...
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... Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time Doc ID 6512 Rev 8 M95040, M95020, M95010 and Table 8 Min. Max. Unit D.C. 5 MHz 90 ...
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... M95040, M95020, M95010 Table 18. AC characteristics (M950x0-W, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV CLQX ...
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... Clock low setup time before HOLD not active Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time Doc ID 6512 Rev 8 M95040, M95020, M95010 Table 11 and Table 9 Min. Max. D. ...
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... M95040, M95020, M95010 Table 20. AC characteristics (M950x0-R, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH t HLCH t CLHL t CLHH ( SHQZ DIS t t CLQV CLQX ...
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... DC and AC parameters Figure 15. Serial input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD 34/43 tSLCH tCH tCHCL tCL tCHDX MSB IN High impedance tHLCH tCLHL tHLQZ Doc ID 6512 Rev 8 M95040, M95020, M95010 tSHSL tCHSH tSHCH tCLCH LSB IN tHHCH tCLHH tHHQV AI01448c AI01447d ...
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... M95040, M95020, M95010 Figure 17. Serial output timing S C tCLQV tCLCH tCLQX Q ADDR D LSB IN tCH tCHCL tCL tQLQH tQHQL Doc ID 6512 Rev 8 DC and AC parameters tSHSL tSHQZ AI01449f 35/43 ...
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... Doc ID 6512 Rev 8 M95040, M95020, M95010 h x 45˚ c 0.25 mm GAUGE PLANE SO-A (1) inches Typ Min 0.0039 0.0492 0.011 0.0067 0.1929 0.189 0.2362 0.2283 0.1535 0.1496 ...
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... M95040, M95020, M95010 Figure 19. TSSOP8 — 8-lead thin shrink small outline, package outline Drawing is not to scale. Table 22. TSSOP8 — 8-lead thin shrink small outline, package mechanical data Symbol N (number of leads) 1. Values in inches are converted from mm and rounded to 4 decimal digits. ...
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... Doc ID 6512 Rev 8 M95040, M95020, M95010 UFDFPN- (1) inches Typ Min Max 0.0217 0.0177 0.0236 0.0008 0 0.002 0.0098 0.0079 0.0118 0.0787 0.0748 ...
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... M95040, M95020, M95010 11 Part numbering Table 24. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM Device function 040 = 4 Kbit (512 x 8) 020 = 2 Kbit (256 x 8) 010 = 1 Kbit (128 x 8) Operating voltage blank = V = 4 2 1.8 to 5.5V CC Package ...
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... Part numbering Table 25. Available M95010 products (package, voltage range, temperature grade) Package SO8N (MN) TSSOP8 (DW) MLP8 (MB) Table 26. Available M95020 products (package, voltage range, temperature grade) Package SO8N (MN) TSSOP8 (DW) MLP8 (MB) Table 27. Available M95040 products (package, voltage range, temperature grade) Package SO8N (MN) TSSOP8 (DW) ...
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... M95040, M95020, M95010 12 Revision history Table 28. Document revision history Date Version 10-May-2000 16-Mar-2001 19-Jul-2001 11-Oct-2001 26-Feb-2002 27-Sep-2002 24-Oct-2002 24-Feb-2003 28-May-2003 25-Jun-2003 21-Nov-2003 02-Feb-2004 01-Mar-2004 05-Oct-2004 s/issuing three bytes/issuing two bytes/ in the 2nd sentence of the Byte 2.2 Write Operation Human Body Model meets JEDEC std (Table 2). Minor adjustments to Figs 7,9,10,11 & ...
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... Figure 20: UFDFPN8 (MLP8) — 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package /W process option removed from ECOPACK text updated. Small text changes. Doc ID 6512 Rev 8 M95040, M95020, M95010 Changes Table 5: Status register format (RDSR). Section 2.8: Supply voltage (VCC) Section 4: Operating features ...
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... M95040, M95020, M95010 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...