M95512-WMN6P STMicroelectronics, M95512-WMN6P Datasheet - Page 18

• Manufacturer Part Number: M95512-WMN6P
• Description: IC EEPROM 512KBIT 5MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95512-WMN6P

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 512K (64K x 8)
• Speed: 5MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8613-5; M95512-WMN6P

Instructions
6.1
6.2
18/48
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 8.
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Figure 9.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Enable (WREN) sequence
Figure
Write Disable (WRDI) sequence
S
C
D
Q
S
C
D
Q
8, to send this instruction to the device, Chip Select (S) is driven low,
9, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 11124 Rev 14
High Impedance
0
1
High Impedance
0
2
Instruction
1
3
2
Instruction
4
3
5
4
6
5
7
6
M95512-DR, M95512-W, M95512-R
7
AI02281E
AI03750D