M25P80-VMN3P/4 NUMONYX, M25P80-VMN3P/4 Datasheet - Page 13

• Manufacturer Part Number: M25P80-VMN3P/4
• Description: IC SRL FLASH 8MBIT 3V SO8 AUTO
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P80-VMN3P/4

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.5
4.6
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P80 boasts the following data protection mechanisms:
In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep Power-
down instruction).
Table 2.
BP2
Status Register
bit
0
0
0
0
Section 6.4: Read Status Register
Power-On Reset and an internal timer (t
inadvertent changes while the power supply is outside the operating specification.
Program, Erase, and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
after the following events:
–
–
–
–
–
–
Software Protected Mode (SPM): The Block Protect bits (BP2, BP1, BP0) allow part of
the memory to be configured as read-only.
Hardware Protected Mode (HPM): The Write Protect (W) signal allows the Block
Protect bits (BP2, BP1, BP0) and the Status Register Write Disable bit (SRWD) to be
protected.
content
BP1
bit
0
0
1
1
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Protected area sizes
BP0
bit
0
1
0
1
none
Upper sixteenth (Sector 15)
Upper eighth (two sectors: 14 and 15)
Upper quarter (four sectors: 12 to 15)
Protected area
(RDSR).
PUW
Memory content
) can provide protection against
All sectors
Lower fifteen-sixteenths (fifteen sectors:
0 to 14)
Lower seven-eighths (fourteen sectors:
0 to 13)
Lower three-quarters (twelve sectors: 0
to 11)
(1)
Unprotected area
(sixteen sectors: 0 to 15)
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