STK17TA8-RF45ITR Cypress Semiconductor Corp, STK17TA8-RF45ITR Datasheet - Page 20

• Manufacturer Part Number: STK17TA8-RF45ITR
• Description: IC NVSRAM 1MBIT 45NS 48SSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of STK17TA8-RF45ITR

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Document #: 001-52039 Rev. *A
Register Map Detail
WDS
WDW
WDT
WIE
AIE
PFIE
0
H/L
P/L
M
M
M
0x1FFF7
0x1FFF6
0x1FFF5
0x1FFF4
0x1FFF4
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit is cleared automatically
once the watchdog timer is reset. The WDS bit is write only. Reading it always will return a 0.
Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out value (WDT5-WDT0). This
allows the user to strobe the watchdog stobe bit without disturbing the time-out value. Set this bit to 0 to allow bits
5-0 to be written.
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents
a multiplier of the 32 Hz count (31.25 ms). The range of time-out values is 31.25 ms (a setting of 1) to 2 seconds
(setting of 3Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the
WDW bit was cleared to 0 on a previous cycle.
Watchdog Interrupt Enable. When set to 1 and a watchdog time-out occurs, the watchdog timer drives the INT pin
as well as setting the WDF flag. When set to 0, the watchdog time-out only sets the WDF flag.
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin as well as setting the AF flag. When set
to 0, the alarm match only affects the AF flag.
Power-Fail Enable. When set to 1, a power failure drives the INT pin as well as setting the PF flag. When set to 0,
the power failure only sets the PF flag.
Reserved For Future Used
High/Low. When set to a 1, the INT pin is driven active high. When set to 0, the INT pin is open drain, active low.
Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approxi-
mately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the Flags register is read.
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value.
Match. Setting this bit to 0 causes the date value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the date value.
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the hours value.
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.
Match. Setting this bit to 0 causes the hours value to be used in the alarm match. Setting this bit to 1 causes the
match circuit to ignore the hours value.
WDS
WIE
D7
D7
D7
D7
D7
M
M
M
(continued)
WDW
AIE
D6
D6
D6
D6
D6
0
0
0
PFIE
D5
D5
D5
D5
10s Alarm Hours
D5
10s Alarm Hours
10s Alarm Date
ABE
D4
D4
D4
D4
D4
Watchdog Timer
Alarm – Hours
Alarm – Hours
Alarm – Day
Interrupt
H/L
D3
D3
D3
D3
D3
WDT
P/L
D2
D2
D2
D2
D2
Alarm Hours
Alarm Hours
Alarm Date
D1
D1
D1
D1
D1
0
STK17TA8
Page 20 of 24
D0
D0
D0
D0
D0
0
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