IDT71016S15Y IDT, Integrated Device Technology Inc, IDT71016S15Y Datasheet - Page 6
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IDT71016S15Y
Manufacturer Part Number
IDT71016S15Y
Description
IC SRAM 1MBIT 15NS 44SOJ
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT71016S20PHG8.pdf
(9 pages)
Specifications of IDT71016S15Y
Format - Memory
RAM
Memory Type
SRAM
Memory Size
1M (64K x 16)
Speed
15ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
44-SOJ
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
71016S15Y
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
AOBE
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Manufacturer:
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Quantity:
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Part Number:
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Manufacturer:
IDT
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Part Number:
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Manufacturer:
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Quantity:
658
Timing Waveform of Read Cycle No. 2
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise t
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, t
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
BHE, BLE
ADDRESS
ADDRESS
BHE
DATA
data to be placed on the bus for the required t
minimum write pulse is as short as the specified t
DATA
DATA
,
BLE
WE
OUT
CS
OE
OUT
CS
IN
PREVIOUS DATA VALID
t
AS
DW
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
WP
t
.
CLZ
(3)
(3)
t
WHZ
t
ACS
t
t
t
AW
BLZ
AA
(5)
t
CW
t
(2)
BE
(3)
t
OLZ
(2)
t
t
(2)
BW
WC
t
RC
(3)
6.42
WP
t
6
OE
t
WP
must be greater than or equal to t
(1)
DATA
t
DW
IN
Commercial and Industrial Temperature Ranges
VALID
DATA
AA
t
DH
t
t
is the limiting parameter.
OW
WR
OUT
(5)
WHZ
+ t
VALID
t
OH
DW
t
CHZ
t
BHZ
t
to allow the I/O drivers to turn off and
OHZ
(3)
(3)
DATA VALID
(3)
t
t
CHZ
BHZ
(5)
(1,2,4)
(5)
3210 drw 08
3210 drw 07
,
,