CY7C1565V18-375BZC Cypress Semiconductor Corp, CY7C1565V18-375BZC Datasheet
CY7C1565V18-375BZC
Specifications of CY7C1565V18-375BZC
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CY7C1565V18-375BZC Summary of contents
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... To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C1561V18), 9-bit words (CY7C1576V18), 18-bit words (CY7C1563V18), or 36-bit words (CY7C1565V18) that [1] burst sequentially into or out of the device. Because data is trans- DD ...
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... D [8:0] 21 Address A (20:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [0] Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Write Write Write Write Address Reg Reg Reg Reg Register Control Logic Read Data Reg Reg. Reg. 16 Reg. Write Write ...
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... Logic Block Diagram (CY7C1563V18 [17:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram (CY7C1565V18 [35:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 ...
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... Pin Configuration The pin configuration for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follow DOFF V V REF DDQ TDO TCK DOFF V V REF DDQ TDO TCK A Note 2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level. Document Number: 001-05384 Rev. *F ...
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... Pin Configuration (continued) The pin configuration for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follow NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK ...
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... CY7C1561V18 arrays each for CY7C1576V18 arrays each 18) for CY7C1563V18 and arrays each of 512K x 36) for CY7C1565V18. Therefore, only 21 address inputs are needed to access the entire memory array of CY7C1561V18 and CY7C1576V18, 20 address inputs for CY7C1563V18, and 19 address inputs for CY7C1565V18 ...
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... Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Pin Description output impedance are set to 0.2 x RQ, where resistor connected [x:0] , which enables the DDQ Page [+] Feedback ...
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... Functional Overview The CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 are synchronous pipelined Burst SRAMs equipped with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port ...
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... CLKIN/CLKIN Source K Source K Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Valid Data Indicator (QVLD) QVLD is provided on the QDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the QDR-II+ device along with data output. This signal is also edge-aligned with the echo clock and follows the timing of any data pin ...
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... The truth table for CY7C1561V18, CY7C1576V18, CY7C1563V18, and CY7C1565V18 follows. Truth Table Operation K RPS WPS [9] Write Cycle: L-H H Load address on the rising edge of K; input write data on two consecutive K and K rising edges. [10] Read Cycle: L-H L (2.5 cycle Latency) Load address on the rising edge of K ...
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... L–H – No data is written into the device during this portion of a write operation. H – L–H No data is written into the device during this portion of a write operation. The write cycle description table for CY7C1565V18 follows. Write Cycle Descriptions BWS BWS BWS BWS K ...
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... TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in page 15 ...
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... TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. ...
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... The state diagram for the TAP controller follows. TAP Controller State Diagram TEST-LOGIC 1 RESET 0 1 TEST-LOGIC/ 0 IDLE Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 [12] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1-DR ...
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... These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the 14. Overshoot: V (AC) < 0.35V (Pulse width less than t IH DDQ 15. All Voltage referenced to Ground. Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 0 Bypass Register Instruction Register ...
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... CS CH 17. Test conditions are specified using the load in TAP AC Test Conditions. t Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Description [17] Figure 2. TAP Timing and Test Conditions 1.8V 50Ω ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Value CY7C1576V18 CY7C1563V18 000 000 00000110100 00000110100 ...
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... Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D ...
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... SRAM behavior. To avoid this, provide 2048 cycles stable clock to relock to the desired clock frequency. REF Figure 3. Power Up Waveforms > 2048 Stable Clock DDQ Stable (< + 0.1V DC per 50 ns) Fix HIGH (tie to V DDQ ) CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 . KC Var Start Normal Operation Page [+] Feedback [+] Feedback ...
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... MHz (min) within 200 ms. During this time V < V and /2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Ambient [18] Temperature ( 0°C to +70°C 1.8 ± 0.1V 1.4V to –40°C to +85°C ...
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... Electrical Characteristics (continued) DC Electrical Characteristics [15] Over the Operating Range Parameter Description [22 Operating Supply Automatic Power down SB1 Current Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Test Conditions V = Max, 333 MHz mA, OUT 1/t MAX CYC x18 x36 300 MHz x8 x9 x18 ...
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... Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V 250Ω, V levels of 0.25V to 1.25V, and output loading of the specified I Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Test Conditions Test Conditions T = 25° MHz ...
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... QVLD signal. QVLD 30. Hold to >V or < Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 400 MHz Description Min Max Min Max Min Max Min Max [25] 1 2.50 8.40 2.66 8.40 0.4 – 0.4 – ...
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... KHKH D10 D11 D12 D13 t QVLD t DOH CLZ Q00 Q01 CCQO t CQOH CCQO t CQOH CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 NOP D30 D32 D33 D31 t QVLD t CQDOH t CQD Q02 Q03 Q20 Q21 Q22 Q23 DON’T CARE UNDEFINED Page CHZ [+] Feedback [+] Feedback ...
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... CY7C1563V18-400BZC CY7C1565V18-400BZC CY7C1561V18-400BZXC CY7C1576V18-400BZXC CY7C1563V18-400BZXC CY7C1565V18-400BZXC CY7C1561V18-400BZI CY7C1576V18-400BZI CY7C1563V18-400BZI CY7C1565V18-400BZI CY7C1561V18-400BZXI CY7C1576V18-400BZXI CY7C1563V18-400BZXI CY7C1565V18-400BZXI 375 CY7C1561V18-375BZC CY7C1576V18-375BZC CY7C1563V18-375BZC CY7C1565V18-375BZC CY7C1561V18-375BZXC CY7C1576V18-375BZXC CY7C1563V18-375BZXC CY7C1565V18-375BZXC CY7C1561V18-375BZI CY7C1576V18-375BZI CY7C1563V18-375BZI CY7C1565V18-375BZI CY7C1561V18-375BZXI CY7C1576V18-375BZXI CY7C1563V18-375BZXI CY7C1565V18-375BZXI Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
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... CY7C1561V18-300BZXI CY7C1576V18-300BZXI CY7C1563V18-300BZXI CY7C1565V18-300BZXI Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) Pb-Free 51-85195 165-Ball Fine Pitch Ball Grid Array ( 1.4 mm) 51-85195 165-Ball Fine Pitch Ball Grid Array ( ...
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... Package Diagram Figure 6. 165-ball FBGA ( 1.4 mm), 51-85195 Document Number: 001-05384 Rev. *F CY7C1561V18, CY7C1576V18 CY7C1563V18, CY7C1565V18 51-85195-*A Page [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY7C1561V18/CY7C1576V18/CY7C1563V18/CY7C1565V18, 72-Mbit QDR™-II+ SRAM 4-Word Burst Archi- tecture (2.5 Cycle Read Latency) Document Number: 001-05384 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE ** 402911 See ECN VEE *A 425251 See ECN VEE *B 437000 See ECN IGS *C 461934 See ECN ...