MD8331-D2G-V18-X-P/Y SanDisk, MD8331-D2G-V18-X-P/Y Datasheet - Page 69

• Manufacturer Part Number: MD8331-D2G-V18-X-P/Y
• Description: IC MDOC G4 2GB 69-FBGA
• Manufacturer: SanDisk

Specifications of MD8331-D2G-V18-X-P/Y

• Format - Memory: FLASH
• Memory Type: FLASH - Nand
• Memory Size: 2G (256M x 8)
• Speed: 33ns
• Interface: Parallel
• Voltage - Supply: 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 69-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MD8831-D2G-V18-X-P/Y; MD8831-D2G-V18-X-P/Y; MD8832-D2G-V18-X-P/Y; MD8832-D2G-V18-X-P/Y

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2.
3.
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6.
7.
69
CE# may be asserted any time before or after OE# is asserted. If CE# is asserted after OE#, all timing relative to OE# asserted will be referenced
instead to the time of CE# asserted.
CE# may be negated any time before or after OE# is negated. If CE# is negated before OE#, all timing relative to OE# negated will be
referenced instead to the time of CE# negated.
Access time 700 ns on the first read cycle when exiting Power-Down Mode if correct data is required from the RAM..
For RAM read cycles, the Address must be held valid until after the data is latched by the host.
A[1] may have no more than 1 transition in the region between t1X(A1) and tsu(A), and may have no transitions between tsu(A) and tho(A).
Does not include output buffer Hi-Z delay (TBD).
No load (CL = 0 pF).
Tsu(A1-OE0)
Tho(OE1-A1)
Tho(OE0-A1)
Tsu(A-OE1)
Tho(A1-D)
Tsu(CE0)
Tho(CE0)
Tho(CE1)
Tsu(CE1)
Trec(OE)
Tho(A-D)
Tw(OE0)
Tacc(A1)
Tcyc(A1)
Trec(A1)
Symbol
Tacc(A)
T
Tloz(D)
Thiz(D)
Tsu(A)
Tho(A)
1X
Tacc
(A1)
Table 10: Standard Interface Read Cycle Timing Parameters
Address to OE#
Address to OE#
OE# low pulse width
OE#
CE#
OE#
OE# or WE#
CE#
time
OE# negated to start of next cycle
Read access time (RAM)
Read access time (all other
addresses)
OE#
OE#
RAM Read access time from A[9:1]
RAM Read access time from A[0]
(IF_CFG=0)
Data hold time from A[9:0] (RAM)
Start of A[1] single transition region
before OE#
Access time from A[1]
A[1] to D output hold time
A[1] to OE#
OE#
OE#
A[1] to start of next cycle
Time between A[1] transitions
to OE#
to WE#
to Address hold time
to CE#
to D driven
to D Hi-Z delay
to A[1] hold time
to A[1] hold time
Data Sheet (Preliminary) Rev. 0.3
1
Description
6
setup time
to CE#
setup time
hold time
or OE#
3
setup time
setup time
1,2
3,7
2
1,8
10
1,4
1
hold time
3
5
1
setup
1
9
2
2
2
DiskOnChip G4 128MB (1Gb)/256MB (2Gb) 1.8V
VCC=1.65-1.95V
Min
-19
27
34
31
20
30
10
33
98
60
—
—
VCCQ=VCC
-8
-8
5
5
3
0
Max
75
33
20
68
39
56
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
92-DS-1105-00