AT17LV040-10TQU Atmel, AT17LV040-10TQU Datasheet - Page 7

• Manufacturer Part Number: AT17LV040-10TQU
• Description: IC CONFIG SEEPROM 4M 3.3V 44TQFP
• Manufacturer: Atmel

Specifications of AT17LV040-10TQU

• Programmable Type: Serial EEPROM
• Memory Size: 4Mb
• Voltage - Supply: 3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP
• Density: 4Mb
• Interface Type: Serial (2-Wire)
• Organization: 4Mx1
• Frequency (max): 10/15MHz
• Write Protection: Yes
• Data Retention: 90Year
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Supply Current: 10mA
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• For Use With: ATDH2225 - CABLE ISP FOR AT17ATDH2200E - CONFIGURATOR PROGRAM BOARD KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2321I–CNFG–2/08
DATA
CLK
WP1
RESET/OE
WP
WP2
CE
GND
CEO
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010/002 devices.
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the
data output driver. The logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed active Low. This document
describes the pin as RESET/OE.
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low). When WP
is Low, the entire memory can be written. When WP is enabled (High), the lowest block of the
memory cannot be written. This pin is only available on AT17LV65/128/256 devices.
WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled
by default due to internal pull-down resistor. This input pin is not used during FPGA loading
operations. This pin is only available on AT17LV512/010 devices.
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low).
Ground pin. A 0.2 µF decoupling capacitor between V
Chip Enable Output (active Low). This output goes Low when the address counter has reached
its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of one device must
be connected to the CE input of the next device in the chain. It will stay Low as long as CE is
Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until
the entire EEPROM is read again. This CEO feature is not available on the AT17LV65 device.
AT17LV65/128/256/512/010/002/040
CC
and GND is recommended.
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