EPC16UC88N Altera, EPC16UC88N Datasheet - Page 19

• Manufacturer Part Number: EPC16UC88N
• Description: IC CONFIG DEVICE 16MBIT 88-UBGA
• Manufacturer: Altera
• Series: EPCr

Specifications of EPC16UC88N

• Programmable Type: In System Programmable
• Memory Size: 16Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 88-UBGA
• Function: Configuration Device
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Mounting: Surface Mount
• Pin Count: 88
• Package Type: uBGA
• Memory Type: Flash
• Clock Frequency: 66.7MHz
• Supply Voltage Range: 3V To 3.6V
• Memory Case Style: BGA
• No. Of Pins: 88
• Operating Temperature Range: 0°C To +70°C
• Access Time: 90ns
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1374; EPC16UC88N

Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
Functional Description
Programmable Configuration Clock
© December 2009 Altera Corporation
f
Table 1–6. Stratix Compression Ratios
The configuration clock (DCLK) speed is user programmable. One of two clock sources
can be used to synthesize the configuration clock; a programmable oscillator or an
external clock input pin (EXCLK). The configuration clock frequency can be further
synthesized using the clock divider circuitry. This clock can be divided by the N
counter to generate your DCLK output. The N divider supports all integer dividers
between 1 and 16, as well as a 1.5 divider and a 2.5 divider. The duty cycle for all clock
divisions other than non-integer divisions is 50% (for the non-integer dividers, the
duty cycle will not be 50%). Refer to
divider unit.
Figure 1–5. Clock Divider Unit
The DCLK frequency is limited by the maximum DCLK frequency the FPGA supports.
The maximum DCLK input frequency supported by the FGPA is specified in the
appropriate FPGA family chapter in the
Logic Utilization
Compression Ratio
% Size Reduction
Note to
(1) These numbers are preliminary. They are intended to serve as a guideline, not a specification.
Table
(Up to 100 MHz)
External Clock
1–6:
Item
10 MHz
33 MHz
50 MHz
66 MHz
Internal Oscillator
(Note 1)
Figure 1–5
Configuration Device
Minimum
Configuration
98%
47%
1.9
Clock Divider Unit
for a block diagram of the clock
Configuration Handbook (Complete Two-Volume Set)
Divide
by N
Handbook.
Average
64%
57%
2.3
DCLK
1–19