XCF32PVOG48C Xilinx Inc, XCF32PVOG48C Datasheet - Page 7

IC PROM SRL 1.8V 32M GATE 48TSOP

XCF32PVOG48C

Manufacturer Part Number
XCF32PVOG48C
Description
IC PROM SRL 1.8V 32M GATE 48TSOP
Manufacturer
Xilinx Inc
Datasheet

Specifications of XCF32PVOG48C

Programmable Type
In System Programmable
Memory Size
32Mb
Voltage - Supply
1.65 V ~ 2 V
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TFSOP (0.472", 12.0mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1458
122-1458-5
122-1458-5

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Platform Flash PROM TAP Characteristics
The Platform Flash PROM family performs both in-system
programming and IEEE 1149.1 Boundary-Scan (JTAG) testing
via a single 4-wire Test Access Port (TAP). This simplifies
system designs and allows standard Automatic Test
Equipment to perform both functions. The AC characteristics
of the Platform Flash PROM TAP are described as follows.
X-Ref Target - Figure 4
TAP AC Parameters
Table 9
Table 9: Test Access Port Timing Parameters
DS123 (v2.18) May 19, 2010
Product Specification
T
T
T
T
T
T
CKMIN
MSS
MSH
DIS
DIH
DOV
Symbol
shows the timing parameters for the TAP waveforms shown in
TMS
TDO
TCK
TDI
R
TCK minimum clock period when V
TMS setup time when V
TMS hold time when V
TDI setup time when V
TDI hold time when V
TDO valid delay when V
T
CKMIN
T
DIS
T
MSS
CCJ
CCJ
CCJ
CCJ
CCJ
Figure 4: Test Access Port Timing
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
= 2.5V or 3.3V
Description
CCJ
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
= 2.5V or 3.3V
T
DIH
T
MSH
TAP Timing
Figure 4
These TAP timing characteristics are identical for both
Boundary-Scan and ISP operations.
Figure
shows the timing relationships of the TAP signals.
T
DOV
4.
Min
67
25
25
8
8
DS123_04_031808
Max
22
Units
ns
ns
ns
ns
ns
ns
7

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