XC17S50APD8C Xilinx Inc, XC17S50APD8C Datasheet - Page 3

• Manufacturer Part Number: XC17S50APD8C
• Description: IC PROM SER 50000 C-TEMP 8-DIP
• Manufacturer: Xilinx Inc

Specifications of XC17S50APD8C

• Programmable Type: OTP
• Memory Size: 500kb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Controlling PROMs
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device mode pins. In Master
Serial mode, the Spartan device automatically loads the
DS078 (v1.10) June 25, 2007
Product Specification
Connecting the Spartan device with the PROM:
The DATA output of the PROM drives the D
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is connected to the
INIT pin of the Spartan device and a pull-up resistor.
This connection assures that the PROM address
counter is reset before the start of any
(re)configuration, even when a reconfiguration is
initiated by a V
The CE input of the PROM is connected to the DONE
pin of the Spartan device and a pull-up resistor. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
R
CC
glitch.
Figure 1: XC17S00A PROM Connections to FPGA in Master Serial Mode
Notes:
1. If the DriveDone configuration option is not active, pull up DONE with a 3.3 kΩ resistor.
M0
M1
M2
Master Serial
Spartan-IIE
Spartan-II/
IN
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
input of
DONE
CCLK
www.xilinx.com
INIT
D
IN
3.3V
configuration program from an external memory. The
XC17S00A PROM has been designed for compatibility with
the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the mode pins are set
to Master Serial mode. Data is read from the PROM
sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial mode provides a simple configuration
interface
and a clock line are required to configure the Spartan
device. Data from the PROM is read sequentially, accessed
via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function D
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan-II/Spartan-IIE family takes care of this
automatically with an on-chip pull-up/down resistor or
keeper circuit.
The one-time-programmable XC17S00A PROM in
Figure 1, page 3
configuration programs. An early DONE inhibits the PROM
data output one CCLK cycle before the Spartan FPGA I/Os
become active.
3.3V
(Figure
CLK
CE
OE/RESET
DATA
1). Only a serial data line, two control lines,
supports automatic loading of
V
V
XC17S00A
CC
CC
PROM
DS078_01_061107
IN
pin on the
3