XC17128EPC20I Xilinx Inc, XC17128EPC20I Datasheet - Page 10

• Manufacturer Part Number: XC17128EPC20I
• Description: IC PROM SER I-TEMP 128K 20-PLCC
• Manufacturer: Xilinx Inc

Specifications of XC17128EPC20I

• Programmable Type: OTP
• Memory Size: 128kb
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AC Characteristics Over Operating Condition When Cascading
DS027 (v3.5) June 25, 2008
Product Specification
Notes:
1.
2.
3.
4.
5.
Symbol
(First PROM)
(First PROM)
Example: If the XC1701L is cascaded to configure an FPGA T
or max CLK frequency = 8 MHz.
Example: For the XC1701L when cascading, the actual T
T
T
T
T
T
RESET/OE
(Cascaded
(Cascaded
AC test load = 50 pF.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
Guaranteed by design, not tested.
All AC parameters are measured with V
For cascaded PROMs:
OCK
OCE
OOE
CDF
CCE
- T
- T
PROM)
PROM)
DATA
DATA
CYC
CAC
CEO
CLK
CE
CE
min = T
R
CLK to data float delay
CLK to CEO delay
CE to CEO delay
RESET/OE to CEO delay
CE to data delay when cascading
max = T
OCK
OCK
T
+ T
OOE
+ T
Description
CCE
Product Obsolete or Under Obsolescence
CCE
(3)
(3)
+ FPGA data setup time (T
First
Bit
.
(2,3)
(3)
T
T
IL
T
OCK
CDF
CCE
= 0.0V and V
Last
Bit
First
Bit
Min
IH
XC17128E,
XC17256E,
DCC
XC1704L,
–
–
–
–
–
XC1702L
XC1701,
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
= 3.0V.
www.xilinx.com
/T
CAC
DSCK
T
DCC
Max
max = 30 ns + 90 ns = 120 ns.
OCE
50
30
35
30
45
n –1
).
= 5 sec, then the actual T
n
XC17128EL,
XC17256EL,
Min
XC17512L
XC1701L,
–
–
–
–
–
Max
50
30
35
30
90
T
CCE
Min
XC1736E,
–
–
–
–
–
XC1765E
CYC
n
T
min = 30 ns + 90 ns + 5 ns = 125 ns,
OCE
Max
n +1
50
30
35
30
60
Min
XC1765EL
–
–
–
–
–
Last
Bit
Max
110
50
30
35
30
DS027_04_071204
Units
ns
ns
ns
ns
ns
10