DP8421AV-20 National Semiconductor, DP8421AV-20 Datasheet - Page 9
![IC CTRLR/DVR CMOS PROGRAM 68PLCC](/photos/6/79/67999/14-68-plcc_sml.jpg)
DP8421AV-20
Manufacturer Part Number
DP8421AV-20
Description
IC CTRLR/DVR CMOS PROGRAM 68PLCC
Manufacturer
National Semiconductor
Datasheet
1.DP8420AV-25.pdf
(58 pages)
Specifications of DP8421AV-20
Controller Type
Dynamic RAM (DRAM)
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP8421AV-20
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3 0 Programming and Resetting
3 2 PROGRAMMING METHODS
3 2 1 Mode Load Only Programming
To use this method the user asserts ML enabling the inter-
nal programming register After ML is asserted a valid pro-
gramming selection is placed on the address bus B0 B1
and ECAS0 inputs then ML is negated When ML is negat-
ed the programming bits are latched into the internal pro-
gramming register and the DP8420A 21A 22A is pro-
grammed see Figure 6 When programming the chip the
controller must not be refreshing RFIP must be high (1) to
have a successful programming
FIGURE 7 CS Access Programming
FIGURE 6 ML Only Programming
(Continued)
9
3 2 2 Chip Selected Access Programming
The chip can also be programmed by performing a chip
selected access To program the chip using this method
ML is asserted then CS is asserted and a valid program-
ming selection is placed on the address bus When AREQ is
asserted the programming bits affecting the wait logic be-
come effective immediately then DTACK is asserted allow-
ing the access to terminate After the access ML is negated
and the rest of the programming bits take effect
TL F 8588 – G3
TL F 8588 – G4