VIPER25LD STMicroelectronics, VIPER25LD Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
VIPER25LD
Manufacturer Part Number
VIPER25LD
Description
IC OFFLINE CONV PWM OVP 16-SOIC
Manufacturer
STMicroelectronics
Series
VIPer™ plusr
Datasheet
1.VIPER25LN.pdf
(40 pages)
Specifications of VIPER25LD
Output Isolation
Isolated
Frequency Range
122 ~ 150kHz
Voltage - Input
8.5 ~ 23.5 V
Voltage - Output
800V
Power (watts)
24W
Operating Temperature
-40°C ~ 150°C
Package / Case
16-SOIC (0.154", 3.90mm Width)
Input Voltage
8.5 V to 23.5 V
Switching Frequency
136 KHz
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
VIPER25LDTR
Manufacturer:
AD
Quantity:
918
Company:
Part Number:
VIPER25LDTR
Manufacturer:
STMicroelectronics
Quantity:
1 975
Operation description
7.7
22/40
Frequency foldback function and valley skipping mode
The switching frequency, in Quasi Resonant mode, is not fixed and it depends on both the
load and the converter’s input voltage. The switching frequency increases when the load
decreases, or when the input voltage mains increases, and vice versa. In principle it could
reach an infinite value. To avoid that, the VIPER25 taps the maximum switching frequency of
the application by its control logic.
The frequency limit is realized with an internal oscillator switching at 136 kHz for VIPER25L
or at 225 kHz for the VIPER25H, sees the parameter F
oscillator is synchronized with power MOSFET turn-on. When the power MOSFET is off, if
the first negative-going edge voltage of the ZCD pin, resulting from transformer’s
demagnetization, appears after at least one oscillator cycle has been completed, the
MOSFET is turned ON and the oscillator re-synchronized.
Otherwise, if the first negative-going edge voltage appears before completing one oscillator
cycle, the signal is ignored. Due to the ringing of the drain voltage, the ZCD pin will
experience another positive-going edge voltage that arms the circuit and a subsequent
negative-going edge voltage. Again, if this appears before the oscillator cycle is complete, it
is ignored, otherwise the MOSFET is turned ON and the oscillator re-synchronized. In this
way, one or more drain ringing cycles will be skipped (
called “valley-skipping mode”) and the switching frequency will be prevented from exceeding
the limit F
Figure 29. Drain ringing cycle skipping as the load is progressively reduced
When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the power
MOSFET is allowed to change with discrete steps of one ringing cycle, while the OFF-time
needed for cycle-by-cycle energy balance could fall in between. Thus one or more longer
switching cycles will be compensated by one or more shorter cycles and vice versa. This
mechanism is natural and there is no appreciable effect on the converter’s performances
and on its output voltage.
The operation described so far does not consider the blanking time T
MOSFET's turn OFF. Actually T
condition is met:
Equation 2
where D is the MOSFET duty cycle. If this condition is not met, the time during which
MOSFET's turn-ON is inhibited is extended beyond T
consequence, the maximum switching frequency will be a little lower than the internal limit
set by the oscillator and valley-skipping mode will take place slightly earlier than expected.
V
DS
T
O N
T
T
o s c
FW
OSClim
T
(limit condition)
V
P
in
= P
.
in'
D
t
Doc ID 15585 Rev 4
≤
V
BLANK
DS
1
−
T
T
OSC
BLANK
T
osc
does not come into play as long as the following
lim
P
in
= P
=
in''
1
< P
−
T
in'
BLANK
OSClim
Figure 29 on page 22
OSClim
•
F
OSC
t
by a fraction of T
on
V
lim
DS
Table 8 on page 8
T
o s c
BLANK
P
in
= P
after power
in' ' '
shows the so
BLANK
< P
in''
VIPER25
. This
. As a
t