NCP1351BPG ON Semiconductor, NCP1351BPG Datasheet - Page 16

• Manufacturer Part Number: NCP1351BPG
• Description: IC CTRLR PWM PROG CM OTP 8DIP
• Manufacturer: ON Semiconductor

Specifications of NCP1351BPG

• Output Isolation: Isolated
• Frequency Range: Adjusting
• Voltage - Input: 9.5 ~ 28 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Number Of Outputs: 1
• Output Voltage: - 0.3 V to + 20 V
• Output Current: 400 mA
• Mounting Style: Through Hole
• Maximum Operating Temperature: + 150 C
• Fall Time: 100 ns
• Rise Time: 90 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

we can easily calculate the timer capacitor value for a given
delay. Suppose we need 40 ms. In that case, the capacitor is
simply:
Select a 100 nF value.
four different options (A, B, C and D), we have graphed
important signals during a fault condition. In versions A and
B, an internal error flag is raised as soon the controller hits
the maximum operating frequency. At this moment, the
external timer capacitor charge begins. If the fault persists,
the timer capacitor hits the fault level and the circuit is either
latched (A) or enters auto-recovery burst mode (B). If the
fault disappears, the timer capacitor is simply reset to 0 V by
an internal switch.
the current feedback imposes a switching frequency roughly
equal to half of the maximum limit. For instance, should the
C timer +
Knowing both the ending voltage and the charge current,
To let the designer understand the behavior behind the
On version C and D, the error flag is asserted as soon as
C1
100n
C1
100n
C
100nF
C
100nF
timer
timer
V
V
CC
CC
I timer T
V timer
Timer
R1
2.5k
Timer
R1
2.5k
FB
FB
Figure 19. The Internal Fault Management Differs Depending on the Considered Version
+
V
V
CC
CC
11.7 m
I
10m
I
10m
D
D
timer
timer
FB
FB
I
I
FB
FB
Reset
Reset
P
P
on
on
5
40 m
I
I
FB
FB
+ 94 nF
I
I
FB
FB
I
Else = High
I
Else = High
FB
FB
Auto-Recovery - B Version
(eq. 16)
< 40 mA ? = Low
< 40 mA ? = Low
http://onsemi.com
Latched - A Version
NCP1351
V
V
timer
timer
+
+
+
+
16
5
5
+
-
+
+
-
+
-
-
designer select a 100 kHz maximum switching frequency,
then the error flag would raise and start the timer for an
operating frequency above ≈ 50 kHz. Below 50 kHz, the
timer pin remains grounded. If we consider a DCM
operation at full load, as the inductor peak current is kept
constant, these 50 kHz correspond to 50% of the maximum
delivered power. If the load stays between 50% and 100% of
its nominal value, the timer continues to charge until it
reaches the final level. In that case, the circuit latches off (C)
or enters auto-recovery (D). This behavior is particularly
well suited for applications where the converter delivers a
moderate average power but is subjected to sudden peak
loading conditions. For instance, a power supply is designed
to permanently deliver 20 W but is sized to deliver 80 W in
peak conditions. During these 80 W power excursions, the
timer will react but will not shut down the power supply. On
the contrary, if a short-circuit appends or if the transient
overload lasts too long, the timer will immediately start to
further shutdown the controller in order to protect both the
application and downstream load.
V
VCC
? Reset
CC
S
R
==
(min)
Q
Q
20ms
Filter
20ms
Filter
DRV Pulses
6V
SCR Delatches When
I
SCR
I
I
to DRV
Stage
CC
CC
V
V
< ICC
CC
CC
CV
CV
CC
CC
latch
+
+
(Few mA)
D
D
aux
L
aux
L
aux
aux