NCP1271P65G ON Semiconductor, NCP1271P65G Datasheet - Page 11

• Manufacturer Part Number: NCP1271P65G
• Description: IC CTRLR PWM CM OVP OTP HV 7DIP
• Manufacturer: ON Semiconductor
• Series: Soft-Skip™r

Specifications of NCP1271P65G

• Output Isolation: Either
• Frequency Range: 55 ~ 69kHz
• Voltage - Input: 9.1 ~ 20 V
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 8-DIP (0.300", 7.62mm), 7 Leads
• Number Of Outputs: 1
• Duty Cycle (max): 80 %
• Output Voltage: - 0.3 V to + 20 V
• Output Current: 800 mA
• Mounting Style: Through Hole
• Switching Frequency: 65 KHz
• Maximum Operating Temperature: + 150 C
• Fall Time: 20 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 30 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Biasing the Controller
HV Pin (Pin 8). This pin is capable of supporting up to
500 V, so it can be connected directly to the bulk capacitor.
Internally, the pin connects to a current source which
rapidly charges V
level is reached, the controller turns on and the transformer
auxiliary winding delivers the bias supply voltage to V
The startup FET is then turned off, allowing the standby
power loss to be minimized. This in−chip startup circuit
minimizes the number of external components and Printed
Circuit Board (PCB) area. It also provides much lower
power dissipation and faster startup times when compared
to using startup resistors to V
needs to be designed to supply a voltage above the V
level but below the maximum V
startup mode. Initially, when V
voltage V
is small (200 uA typical). The current goes higher (4.1 mA
typical) when V
illustrated in Figure 23. The dual startup feature protects
the device by limiting the maximum power dissipation
when the V
slightly increases the total time to charge V
generally not noticeable.
During startup, the Vcc bias voltage is supplied by the
For added protection, the NCP1271 also include a dual
4. Latched Shutdown – When the Skip/latch pin (Pin
5. Non−Latched Shutdown – If the FB pin is pulled
cleared after the double hiccup, then the application
restarts. If not, then the process is repeated.
1) voltage is pulled above 8.0 V for more than
13 ms, the NCP1271 goes into latchoff shutdown.
The output is held low and V
mode until the latch is reset. The reset can only
occur if Vcc is allowed to fall below V
(4.0 V typical). This is generally accomplished by
unplugging the main input AC source.
below the skip level, then the device will enter a
non−latched shutdown mode. This mode disables
the driver, but the controller automatically recovers
when the pulldown on FB is released. Alternatively,
Vcc can also be pulled low (below 190 mV) to
shutdown the controller. This has the added benefit
of placing the part into a low current consumption
mode for improved power savings.
inhibit
CC
(600 mV typical), the startup current source
pin (Pin 6) is accidentally grounded. This
CC
CC
goes above V
to its V
CC(on)
CC
CC
. The auxiliary winding
CC
inhibit
CC
level of 20 V.
is below the inhibit
threshold. After this
stays in hiccup
. This behavior is
CC(reset)
CC
, but it is
http://onsemi.com
CC(off)
CC.
11
V
circuit. An undervoltage lockout (UVLO) comparator
monitors the V
V
V
turned back on and charges V
V
cycle is repeated twice to minimize power dissipation in
4.1 mA
200 uA
CC
CC(off)
CC(latch)
CC
Figure 24 illustrates the block diagram of the startup
During double hiccup operation, the Vcc level falls to
Figure 23. Startup Current at Various V
turn on internal bias
then slowly collapses back to the V
Double Hiccup Mode
Counter
, then the controller enters “double hiccup mode.”
4.1 mA when Vcc > 0.6 V
200 uA when Vcc < 0.6 V
B2
(5.8 V typical). At this point, the startup FET is
Startup current
double
hiccup
Q
&
Figure 24. V
0.6 V
CC
S
R
supply voltage. If V
turn off
UVLO
+
+
−
CC
−
20V
9.1 V
V
12.6/
5.8 V
CC
CC(latch)
Management
to V
CC(on)
8
6
CC(latch)
Vcc
HV
V
(12.6 V typical).
CC
CC(on)
CC
V
bulk
falls below
Levels
level. This
V
CC