NCP1217AD100R2 ON Semiconductor, NCP1217AD100R2 Datasheet - Page 12

• Manufacturer Part Number: NCP1217AD100R2
• Description: IC CTRLR PWM CM OVP HV 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCP1217AD100R2

• Output Isolation: Isolated
• Frequency Range: 90 ~ 110kHz
• Voltage - Input: 10 ~ 16 V
• Operating Temperature: 0°C ~ 150°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Number Of Outputs: 1
• Duty Cycle (max): 46.5 %
• Output Current: 500 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 100 KHz
• Maximum Operating Temperature: + 150 C
• Fall Time: 20 ns
• Rise Time: 60 ns
• Synchronous Pin: No
• Topology: Flyback
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 22. Inserting a Resistor in Series with the Current
a duty cycle max at 74%. Over a 65 kHz frequency, for
instance, it corresponds to a 254 mV/ms ramp. In our
FLYBACK design, let’s suppose that our primary
inductance Lp is 350 mH, delivering 12 V with a Np:Ns ratio
of 1:0.1. The OFF time primary current slope is thus given
by:
projected over an Rsense of 0.1 Ω, for instance. If we select
75% of the downslope as the required amount of ramp
compensation, then we shall inject 27 mV/ms. Our
internal compensation being of 254 mV/ms, the divider
ratio (divratio) between Rcomp and the 19 kΩ is 0.106.
A
19 k · divratio
(1--divratio)
In the NCP1217, the ramp features a swing of 2.9 V with
Sense Information Brings Ramp Compensation
few
(Vout + Vf) ·
+
--
Setpoint
From
lines
Lp
= 2.26 kΩ
L.E.B.
of
Duty Cycle Typ = 74%
Np
Ns
= 371 mA∕ms
algebra
.
19 k
CS
2.9 V
0 V
to
Rcomp
or
determine
37 mV∕ms
Rsense
Rcomp:
http://onsemi.com
when
12
Latching Off the NCP1217
through a simple PNP bipolar transistor as depicted by
Figure 23. When OFF, Q1 is transparent to the operation.
When forward biased, the transistor pulls the Adj pin toward
V
above the latching level (typical 3.1 V). Figure 23 shows
how to wire the bipolar transistor to activate the latchoff. A
typical candidate for Q1 could be an MMBT3906 from
ON Semiconductor.
CC
Total latched shutdown can easily be implemented
Off
Figure 23. A Simple Bipolar Transistor Totally
and permanently latches- -off the IC as soon Vadj goes
Disables the IC
Q1
Rlimit
1
2
3
4
V
CC
8
7
6
5
CV
CC