AS1120 austriamicrosystems, AS1120 Datasheet - Page 6

• Manufacturer Part Number: AS1120
• Description: IC LCD DVR 46 SEGMENTS 64-TQFP
• Manufacturer: austriamicrosystems

Specifications of AS1120

• Display Type: LCD
• Configuration: 46 Segment
• Interface: Parallel/Serial
• Current - Supply: 5µA
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -

AS1120
Datasheet - D e t a i l e d D e s c r i p t i o n
7 Detailed Description
The AS1120 can drive up to 46 LCD segments and multiple AS1120 devices can be cascaded (see Figure 8 on page
9) to increase the number of LCD segments.
Note: Due to the accurate delay balance between the backplane input, backplane output, and the LCD segments, it
is possible to mix segments of different display crystal types.
Shift Register
Data accesses are made serially via pins DATAIN and CLKIN. At each CLKIN rising edge the signal present at DATAIN
pin is shifted in the first bit of the internal shift register and the other bits are shifted ahead of the first bit.
To cascade multiple AS1120 devices (see Figure 8 on page 9), the last bit of the internal shift register is presented at
pin DATAOUT at the falling edge of the same CLKIN pulse. The LSB is entered first while MSB is the last bit to be
shifted into the shift register.
Note: The shift register is cleared at when the AS1120 is reset.
Latch Register and Error
When a signal is applied at pin LOAD, data present in the shift register is latched into the internal latch register and
presented to the LCD output segments (LCD[0:45]), also passing through an XOR gate with the backplane signal
(BPLIN). The XOR function is necessary to generate the appropriate signals to drive the LCD segments.
Note: At reset the latch register is cleared, thus no LCD segment will be active at power-on.
Synchronous Mode
Data is shifted into the internal shift register at the rising edge of the CLKIN signal. To load the shift register all 46 data
bits are clocked into the register at the rising edge of CLKIN (see Figure 4). The LOAD signal has to be set high for 8
CLKIN periods before the end of the 46 bits. The display will be updated at the 8th CLKIN rising edge after LOAD goes
high as is shown in Figure 4.
Note: During synchronous mode, a clock on BPLIN must be applied to avoid the risk of damaging the LCD crystal.
Figure 4. Synchronous Mode Timing Diagram
46 CLKIN Cycles
8 CLKIN Cycles
LOAD
DATAIN
X
X
LD45 LD44LD43
LD10
LD9
LD8
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
Stop
CLKIN
BPLIN
Display
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