MCP3906A-I/SS Microchip Technology, MCP3906A-I/SS Datasheet - Page 14

• Manufacturer Part Number: MCP3906A-I/SS
• Description: IC POWER METERING-1 PHASE 24SSOP
• Manufacturer: Microchip Technology

Specifications of MCP3906A-I/SS

• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.85V
• Current - Supply: 2.7mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• Brief Features: Active Real Power Pulse Output, Ultra Low Drift
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: SSOP
• No. Of Pins: 24
• Svhc: No
• Mounting Style: SMD/SMT
• Ic Function: Single Phase Energy Metering
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP3905RD-PM1 - REFERENCE DESIGN FOR MCP3905MCP3905EV - BOARD DEMO FOR MCP3905
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MCP3905A/05L/06A
voltage reference source impedance is typically 4 kΩ,
which enables this voltage reference to be overdriven
by an external voltage reference source.
If an external voltage reference source is connected to
the REFIN/OUT pin, the external voltage will be used
as the reference for both current and voltage channel
ADCs. The voltage across the source resistor will then
be the difference between the internal and external
voltage. The allowed input range for the external
voltage source goes from 2.2V to 2.6V for accurate
measurement error. A V
will cause additional heating and power consumption
due to the source resistor, which might affect measure-
ment error.
4.4
The MCP3905A/05L/06A devices contain an internal
POR circuit that monitors analog supply voltage AV
during operation. This circuit ensures correct device
startup at system power-up and system power-down
events. The POR circuit has built-in hysteresis and a
timer to give a high degree of immunity to potential
ripple and noise on the power supplies, allowing proper
settling of the power supply during power-up. A 0.1 µF
decoupling capacitor should be mounted as close as
possible to the AV
immunity
Information”).
The threshold voltage is typically set at 4V, with a
tolerance of about ±5%. If the supply voltage falls below
this threshold, the MCP3905A/05L/06A devices will be
held in a Reset condition (equivalent to applying logic
‘0’ on the MCLR pin). The typical hysteresis value is
approximately 200 mV in order to prevent glitches on
the power supply.
Once a power-up event has occurred, an internal timer
prevents the part from outputting any pulse for approx-
imately 1s (with MCLK = 3.58 MHz), thereby prevent-
ing potential metastability due to intermittent resets
caused by an unsettled regulated power supply.
Figure 4-3
power-up and a power-down event in the typical condi-
tions.
DS22011A-page 14
Power-On Reset (POR)
illustrates the different conditions for a
(see
DD
pin, providing additional transient
Section 5.0
REF
value outside of this range
“Applications
DD
FIGURE 4-3:
4.5
The active real-power value is extracted from the DC
instantaneous power. Therefore, any DC offset
component present on Channel 0 and Channel 1
affects the DC component of the instantaneous power
and will cause the real-power calculation to be
erroneous. In order to remove DC offset components
from the instantaneous power signal, a high-pass filter
has been introduced on each channel. Since the high-
pass filtering introduces phase delay, identical high-
pass filters are implemented on both channels. The
filters are clocked by the same digital signal, ensuring
a phase difference between the two channels of less
than one MCLK period. Under typical conditions
(MCLK = 3.58 MHz), this phase difference is less than
0.005°, with a line frequency of 50 Hz. The cut-off
frequency of the filter (4.45 Hz) has been chosen to
induce minimal gain error at typical line frequencies,
allowing sufficient settling time for the desired applica-
tions. The two high-pass filters can be disabled by
applying logic ‘0’ to the HPF pin.
FIGURE 4-4:
(MCLK = 3.58 MHz).
DEVICE
MODE
AV
4.2V
5V
4V
0V
DD
-10
-15
-20
-25
-30
-35
-40
-5
0
0.1
High-Pass Filters and Multiplier
RESET
PULSE
OUT
NO
1s
1
Power-on Reset Operation.
HPF Magnitude Response
Frequency (Hz)
© 2006 Microchip Technology Inc.
OPERATION
PROPER
10
100
RESET
1000
Time