ADE7751AN Analog Devices Inc, ADE7751AN Datasheet - Page 12

• Manufacturer Part Number: ADE7751AN
• Description: IC ENERGY METERING DETEC 24-PDIP
• Manufacturer: Analog Devices Inc

Specifications of ADE7751AN

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Meter Type: Single Phase
• Lead Free Status / Rohs Status: Not Compliant

ADE7751
Figure 7 shows two typical connections for Channel V2. The first
option uses a PT (potential transformer) to provide complete isola-
tion from the mains voltage. In the second option, the ADE7751
is biased around the neutral wire and a resistor divider is used to
provide a voltage signal that is proportional to the line voltage.
Adjusting the ratio of Ra and Rb is also a convenient way of
carrying out a gain calibration on the meter.
POWER SUPPLY MONITOR
The ADE7751 contains an on-chip power supply monitor. The
analog supply (AV
If the supply is less than 4 V
This is useful to ensure correct device start up at power-up and
power-down. The power supply monitor has built-in hysteresis
and filtering. This gives a high degree of immunity to false
triggering due to noisy supplies.
As can be seen in Figure 8, the trigger level is nominally set at 4 V.
The tolerance on this trigger level is about 5%. The power supply
and decoupling for the part should be such that the ripple at AV
does not exceed 5 V
PHASE
PHASE
INTERNAL
RESET
Figure 7. Typical Connections for Channel 2
NEUTRAL
NEUTRAL
Figure 8. On-Chip Power Supply Monitor
AV
5V
4V
0V
DD
RESET
Ra
DD
VR
Rb
) is continuously monitored by the ADE7751.
CT
NOTE
Ra
Rb + VR = R f
5% as specified for normal operation.
C f
AGND
660mV
R f ;
ACTIVE
660mV
TIME
5%, the ADE7751 will be reset.
R f
R f
R f
RESET
C f
C f
C f
V2P
V2N
V2P
V2N
DD
–12–
HPF and Offset Effects
Figure 9 shows the effect of offsets on the real power calculation. As
shown in Figure 9, an offset on Channel 1 and Channel 2 will
contribute a dc component after multiplication. Since this dc
component is extracted by the LPF and used to generate the real
power information, the offsets will have contributed a constant
error to the real power calculation. This problem is easily avoided by
enabling the HPF (i.e., pin AC/DC is set logic high) in Channel 1.
By removing the offset from at least one channel, no error component
can be generated at dc by the multiplication. Error terms at cos( t)
are removed by the LPF and the digital-to-frequency conversion—
see Digital-to-Frequency Conversion section.
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 10 and 11 show the phase error between chan-
nels with the compensation network activated. The ADE7751
is phase compensated up to 1 kHz as shown. This will ensure
correct active harmonic power calculation even at low-power factors.
Figure 10. Phase Error Between Channels (0 Hz to 1 kHz)
–0.10
–0.05
V
0.30
0.25
0.20
0.15
0.10
0.05
OS
0
0
V
I
V
OS
2
Figure 9. Effect of Channel Offsets on the
Real Power Calculation
V
V
cos(
I
100
0
2
I
I
200
OS
t
)
V
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
OS
300
V
cos(
OS
I
V
FREQUENCY – Hz
I
OS
FREQUENCY – RAD/S
400
OS
OS
t
)
V
I
I
500
V
V
OS
cos(
2
2
600
I
I
700
t
)
cos(
cos(
I
800
OS
2
t
t
)
900 1000
)
REV. 0