LTC4242IUHF#PBF Linear Technology, LTC4242IUHF#PBF Datasheet - Page 11

• Manufacturer Part Number: LTC4242IUHF#PBF
• Description: IC CTRLR HOTSWAP DUAL-SLOT 38QFN
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LTC4242IUHF#PBF

• Applications: General Purpose, PCI Express
• Internal Switch(s): No
• Voltage - Supply: 2.7 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 38-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

OPERATIO
The Functional Diagram displays the main functional ele-
ments of this device. The LTC4242 is designed to control
the power for two independent slots on a PCI Express
backplane, allowing two boards to be safely inserted and
removed. During normal operation, the charge pump
sources 9µA to turn on the gate of the external N-chan-
nel MOSFETs to pass power to the load. The gates of the
external MOSFETs are clamped about 5.5V above their
sources. The gates of the AUX FETs rise at a slew rate of
about 1.25V/ms to control the inrush current.
The electronic circuit breaker (ECB) comparator and ana-
log current limit (ACL) amplifi er monitor the load current
using the difference between the V
The threshold of the ACL is set at 2x the ECB threshold.
The ACL amplifi er limits the current in the load by reduc-
ing the gate-to-source voltage of the external MOSFETs
in an active control loop. When an overcurrent condition
persists for more than 20µs, the MOSFETs are shut off to
prevent overheating. FAULT is latched low to signal that
an overcurrent condition has occurred on the external
MOSFETs controlling the main channels.
The AUX FET’s control circuitry has a circuit breaker that
trips at 550mA after 20µs. It also incorporates an active
current limit amplifi er that would limit the current fl ow-
ing in the AUX FET to about 1.65A. A thermal shutdown
circuit shuts off the AUX FET when the die temperature
rises above 150°C. AUXFAULT is latched low to signal
APPLICATIO S I FOR ATIO
The typical LTC4242 application is in a backplane or moth-
erboard that controls power to two PCI Express slots. The
device reports fault and power good status to the system
hot plug controller (HPC).
The basic LTC4242 application circuit is shown in Fig-
ure 1. Discussion begins with board presence detection
in a PCI Express system, the normal turn on and off
sequence, the various fault conditons and recovery from
fault situations. The force on operation is discussed next
followed by the considerations for PCB layout. External
component selection is discussed in detail in the Design
Example section.
U
U
U
IN
W
and SENSE voltage.
U
an overcurrent conditon on the internal FET or thermal
shutdown has occurred.
When the switches are off (both internal and external),
the OUT pins are discharged to ground through internal
N-channel transistors.
The output voltages are monitored using the OUT pins
and the PG comparators to determine if the voltage
is valid. The power good conditon is signaled by the
PGOOD/AUXPGOOD pins using open-drain pull-down
transistors.
The Functional Diagram shows the monitoring blocks of
the LTC4242. The group of comparators in the system
control includes the UVLO, ON and EN comparators.
These comparators are used to determine if the external
conditions are valid prior to turning on the switches. But
fi rst the undervoltage lockout circuit (UVLO) must validate
the input supplies and the main supply V
the power up initialization to the logic circuits.
The FON inverter in the system control is used for op-
erating the LTC4242 in diagnostic mode. In this mode
of operation, all pass transistors are forced to turn on,
ignoring the undervoltage, circuit breaker/current limit-
ing status and input commands. However, if V
below its UVLO voltage, all switches would be shut off,
regardless of FON.
Board Presence Detect
In PCI Express systems, the system board connector uses
two signals, PRSNT1 and PRSNT2, to detect the pres-
ence of a board and ensure a fully inserted board in the
connector as shown in Figure 2. PRSNT2 is routed to the
system HPC. Upon a board insertion into the connector,
a turn-on command is generated by the HPC to LTC4242
after a programmed HPC debounce delay, as shown in
Figure 1. Another method to generate the debounce delay
is through the delay network shown in Figure 3.
LTC4242
CC
and generate
CC
11
drops
4242f