LTC4257IS8-1 Linear Technology, LTC4257IS8-1 Datasheet - Page 17

• Manufacturer Part Number: LTC4257IS8-1
• Description: IC CONTROLLER POE INTERFAC 8SOIC
• Manufacturer: Linear Technology
• Type: Power over Ethernet Switch (PoE)r

Specifications of LTC4257IS8-1

• Applications: IP Phones, Power over LAN, Network Routers and Switches
• Internal Switch(s): Yes
• Current Limit: 350mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
Signature Disable Interface
To disable the 25k signature, connect the SIGDISA pin to the
GND pin. Alternately, SIGDISA can be driven high with
respect to V
circuit is shown in Figure 9, option 2. Note that the SIGDISA
input resistance is relatively large and the threshold voltage
is fairly low. Because of high voltages present on the printed
circuit board, leakage currents from the GND pin could
inadvertently pull SIGDISA high. To insure trouble-free
operation, use high-voltage layout techniques in the vicinity
of SIGDISA. If unused, connect SIGDISA to V
Load Capacitor
The IEEE 802.3af specification requires that the PD main-
tain a minimum load capacitance of 5µF. It is permissible
to have a much larger load capacitor and the LTC4257-1
can charge very large load capacitors before thermal
issues become a problem. However, the load capacitor
must not be too large or the PD design may violate IEEE
802.3af requirements.
If the load capacitor is too large there can be a problem with
inadvertent power shutdown by the PSE. Consider the fol-
lowing scenario. If the PSE is running at – 57V (maximum
allowed) and the PD has been detected and powered up,
the load capacitor will be charged to nearly – 57V. If for
some reason the PSE voltage suddenly is reduced to – 44V
(minimum allowed), the input bridge will reverse bias and
PD power will be supplied solely by the load capacitor.
Depending on the size of the load capacitor and the DC load
of the PD, the PD will not draw any power from the PSE
for a period of time. If this period of time exceeds the IEEE
802.3af 300ms disconnect delay, the PSE may remove
power from the PD. For this reason, it is necessary to
evaluate the load capacitance and load current to ensure
that inadvertent shutdown cannot occur.
Very small output capacitors (≤10µF) will charge very
quickly in current limit. The rapidly changing voltage at
the output may reduce the current limit temporarily,
causing the capacitor to charge at a somewhat reduced
rate. Conversely, charging very large capacitors may
cause the current limit to increase slightly. In either case,
once the output voltage reaches its final value, the input
current limit will be restored to its nominal value.
IN
. An example of a signature disable interface
U
U
W
IN
U
.
Maintain Power Signature
In an IEEE 802.3af system, the PSE uses the maintain
power signature (MPS) to determine if a PD continues to
require power. The MPS requires the PD to periodically
draw at least 10mA and also have an AC impedance less
than 26.25kΩ in parallel with 0.05µF. The PD application
circuits shown in this data sheet meet the requirements
necessary to maintain power. If either the DC current is
less than 10mA or the AC impedance is above 26.25kΩ,
the PSE might disconnect power. The DC current must be
less than 5mA and the AC impedance must be above 2MΩ
to guarantee power will be removed.
Layout
The LTC4257-1 is relativity immune to layout problems.
Excessive parasitic capacitance on the R
be avoided. If using the DD package, include an electrically
isolated heat sink to which the exposed pad on the bottom
of the package can be soldered. For optimum thermal
performance, make the heatsink as large as possible.
Voltages in a PD can be as large as – 57V, so high voltage
layout techniques should be employed.
The load capacitor connected between Pins 5 and 8 of the
LTC4257-1 can store significant energy when fully charged.
The design of a PD must ensure that this energy is not
inadvertently dissipated in the LTC4257-1. The polarity-
protection diode(s) prevent an accidental short on the
cable from causing damage. However, if the V
shorted to the GND pin inside the PD while the load
capacitor is charged, current will flow through the para-
sitic body diode of the internal MOSFET and may cause
permanent damage to the LTC4257-1.
Electro Static Discharge and Surge Suppression
The LTC4257-1 is specified to operate with an absolute
maximum voltage of – 100V and is designed to tolerate
brief overvoltage events. However, the pins that interface
to the outside world (primarily V
see peak voltages in excess of 10kV. To protect the
LTC4257-1, it is highly recommended that a transient
voltage suppressor be installed between the bridge and
the LTC4257-1 (D3 in Figure 2).
IN
and GND) can routinely
LTC4257-1
CLASS
pin should
IN
17
pin is
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