ADM1073ARU Analog Devices Inc, ADM1073ARU Datasheet - Page 14

• Manufacturer Part Number: ADM1073ARU
• Description: IC CTRLR HOTSWAP -48V 14TSSOP
• Manufacturer: Analog Devices Inc
• Type: Hot-Swap Controllerr

Specifications of ADM1073ARU

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: -35 V ~ -80 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP (0.173", 4.40mm Width)
• For Use With: EVAL-ADM1073MEB - BOARD EVAL MICRO FOR ADM1073EVAL-ADM1073EB - BOARD EVALUATION FOR ADM1073
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADM1073
When the device detects that the supply voltage is valid, it
ramps up the GATE voltage until the FET turns on and the load
current increases. The ADM1073 monitors the level of the
current flowing through the FET by sensing the voltage across
the external sense resistor, R
reaches 100 mV, the GATE pin is actively controlled, limiting
the load current. In this way, the maximum current permitted to
flow through the load is set by the choice of R
If a change in the level of the supply voltage causes the voltage
on UV to fall below the undervoltage falling threshold (V
or the voltage on OV to rise above the overvoltage rising
threshold (V
BOARD REMOVAL
If the board is removed from a card cage, the voltage on the UV
pin falls to zero (that is, outside operating range) and the GATE
drive is de-asserted, turning off the FET.
CONTROLLING THE CURRENT
The ADM1073 features the following current control functions:
•
•
•
•
•
In the following sections, five distinct system operating
conditions are described with reference to the current control
features.
Startup into Nominal Load Capacitance
Once the supply voltage has exceeded the UV threshold, and
following the 0.6 ms UV filter time, the current to the load
ramps up linearly as the capacitor on the Soft Start (SS) pin is
charged to 2.5 V. At the same time, current is sourced into the
capacitor on the TIMER pin, both from an on-chip source and
via the drain resistor. Once the soft start voltage has reached
2.5 V, the current to the load is limited to I
Assuming that the values of R
have been chosen to allow the load capacitance to charge within
one ON period (t
before the voltage on TIMER reaches 2.5 V. At this point, the
current to the load decreases, and the FET gate voltage increases
to V
Startup into Load with Large Capacitance
If the load capacitance is sufficiently large that to charge it fully
in one attempt would compromise the FET’s SOA, consecutive
maximum current events may be used. The use of this tech-
nique assumes that the load is not yet enabled, so negligible load
current is demanded. The initial current profiling is identical to
that for startup into a nominal load capacitance. If the charge
passed to the load in time t
SS
Precision maximum current limit
Controlled time in current limit
Limited number of consecutive maximum current events
Current limit profiling—soft start
Overcurrent fast limit
, connecting the supply to the load.
OVR
), then the gate drive is disabled.
ON
period), the load capacitor is fully charged
ON
SENSE
with maximum current flowing is
SENSE
. When the SENSE voltage
and the TIMER capacitance
MAX
SENSE
(100 mV/R
.
UVF
SENSE
),
Rev. 0| Page 14 of 24
).
insufficient to fully charge the load capacitance, at the end of
the t
current. The ADM1073 now controls the FET gate to zero for a
time t
sink to discharge the TIMER capacitance to 0.5 V. At the end of
time t
profile. In this way, a large load capacitance can be charged
using consecutive current limit periods. The external compo-
nents should be chosen to ensure that the capacitance is fully
charged within seven TIMER periods, if the default limited
consecutive retry mode is used.
Startup into a Short Circuit or over Current Fault
The load might demand large currents at initial connection. The
ADM1073 follows the Soft Start current profile as described for
startup into a nominal load. The current is limited at I
time t
gate is held low for time t
start current profile. The ADM1073 cycles through 7 retries,
after which it latches the FET off, assuming the default limited
consecutive retry mode is used.
Voltage Step during Normal Operation
Once the load capacitance is charged at initial board insertion
and a PWRGD signal is issued by the ADM1073, the load
begins to demand current. Therefore, following a step increase
in the magnitude of the supply voltage, not all the FET current
is available for charging of the load capacitance. Because the
FET is fully on following a step in the supply voltage, the
current increases immediately from I
the load capacitance. If the current remains below the fast
current limit, the FET gate drive amplifier controls it back to
I
strongly pulled down and back into regulation with the current
at I
the load current and I
charge the load capacitance. External components should be
chosen to ensure that any expected step size leads to a
requirement of less than time t
Short Circuit or Overcurrent Fault during Operation
If a short circuit or an overcurrent fault occurs during normal
operation, the FET is fully on and initially allows increased
current to flow. If the current remains below the fast current
limit, the FET gate drive amplifier controls it back to I
current exceeds the fast current limit, the FET gate is strongly
pulled down and back into regulation with the current at I
Following a period, t
for a time t
profile. If the fault persists, the ADM1073 cycles through 7
retries before latching off. If the fault clears within the 7-retry
period, the ADM1073 controls the FET gate high to allow
normal operation to continue.
MAX
MAX
. If the current exceeds the fast current limit, the FET gate is
ON
OFF
OFF
ON
. The size of the voltage step and the headroom between
period the load capacitance is still demanding maximum
, determined by the time taken for the on-chip current
, the device retries, again following the soft start current
following which the FET gate is pulled low. The FET
OFF
, then retries following the soft start current
ON
MAX
, the ADM1073 pulls the FET gate low
OFF
determine the time required at I
, before retrying, again with the soft
ON
to charge the load capacitance.
LOAD
to supply charge to
MAX
MAX
. If the
for
MAX
MAX
to
.